237 lines
6.1 KiB
Markdown
237 lines
6.1 KiB
Markdown
;; Scheduling description for Renesas SH4a
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;; Copyright (C) 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GNU CC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GNU CC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; The following description models the SH4A pipeline
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;; using the DFA based scheduler.
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(define_automaton "sh4a")
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(define_cpu_unit "sh4a_ex" "sh4a")
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(define_cpu_unit "sh4a_ls" "sh4a")
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(define_cpu_unit "sh4a_fex" "sh4a")
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(define_cpu_unit "sh4a_fls" "sh4a")
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(define_cpu_unit "sh4a_mult" "sh4a")
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(define_cpu_unit "sh4a_fdiv" "sh4a")
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;; Decoding is done on the integer pipeline like the
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;; sh4. Define issue to be the | of the two pipelines
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;; to control how often instructions are issued.
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(define_reservation "ID_or" "sh4a_ex|sh4a_ls")
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(define_reservation "ID_and" "sh4a_ex+sh4a_ls")
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;; =======================================================
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;; Locking Descriptions
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;; Sh4a_Memory access on the LS pipeline.
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(define_cpu_unit "sh4a_memory" "sh4a")
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;; Other access on the LS pipeline.
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(define_cpu_unit "sh4a_load_store" "sh4a")
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;; The address calculator used for branch instructions.
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;; This will be reserved after "issue" of branch instructions
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;; and this is to make sure that no two branch instructions
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;; can be issued in parallel.
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(define_reservation "sh4a_addrcalc" "sh4a_ex")
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;; =======================================================
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;; Reservations
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;; Branch (BF,BF/S,BT,BT/S,BRA,BSR)
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;; Group: BR
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;; Latency when taken: 2
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(define_insn_reservation "sh4a_branch" 2
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "cbranch,jump"))
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"ID_or+sh4a_addrcalc")
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;; Jump (JSR,JMP,RTS)
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;; Group: BR
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;; Latency: 3
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(define_insn_reservation "sh4a_jump" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "return,jump_ind"))
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"ID_or+sh4a_addrcalc")
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;; RTE
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;; Group: CO
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;; Latency: 3
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(define_insn_reservation "sh4a_rte" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "rte"))
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"ID_and*4")
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;; EX Group Single
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;; Group: EX
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;; Latency: 0
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(define_insn_reservation "sh4a_ex" 0
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "insn_class" "ex_group"))
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"sh4a_ex")
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;; MOVA
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;; Group: LS
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;; Latency: 1
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(define_insn_reservation "sh4a_mova" 1
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "mova"))
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"sh4a_ls+sh4a_load_store")
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;; MOV
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;; Group: MT
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;; Latency: 0
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;; ??? not sure if movi8 belongs here, but that's where it was
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;; effectively before.
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(define_insn_reservation "sh4a_mov" 0
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "move,movi8,gp_mac"))
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"ID_or")
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;; Load
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;; Group: LS
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;; Latency: 3
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(define_insn_reservation "sh4a_load" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "load,pcload,mem_mac"))
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"sh4a_ls+sh4a_memory")
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(define_insn_reservation "sh4a_load_si" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "load_si,pcload_si"))
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"sh4a_ls+sh4a_memory")
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;; Store
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;; Group: LS
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;; Latency: 0
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(define_insn_reservation "sh4a_store" 0
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "store,fstore,mac_mem"))
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"sh4a_ls+sh4a_memory")
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;; CWB TYPE
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;; MOVUA
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;; Group: LS
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;; Latency: 3
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(define_insn_reservation "sh4a_movua" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "movua"))
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"sh4a_ls+sh4a_memory*2")
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;; Fixed point multiplication (single)
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;; Group: CO
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;; Latency: 2
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(define_insn_reservation "sh4a_smult" 2
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "smpy"))
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"ID_or+sh4a_mult")
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;; Fixed point multiplication (double)
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;; Group: CO
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;; Latency: 3
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(define_insn_reservation "sh4a_dmult" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "dmpy"))
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"ID_or+sh4a_mult")
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(define_insn_reservation "sh4a_mac_gp" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "mac_gp"))
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"ID_and")
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;; Other MT group instructions(1 step operations)
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;; Group: MT
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;; Latency: 1
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(define_insn_reservation "sh4a_mt" 1
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "mt_group"))
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"ID_or")
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;; Floating point reg move
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;; Group: LS
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;; Latency: 2
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(define_insn_reservation "sh4a_freg_mov" 2
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "fmove"))
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"sh4a_ls,sh4a_fls")
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;; Single precision floating point computation FCMP/EQ,
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;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG
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;; Group: FE
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;; Latency: 3
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(define_insn_reservation "sh4a_fp_arith" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "fp,fp_cmp,fpscr_toggle"))
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"ID_or,sh4a_fex")
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(define_insn_reservation "sh4a_fp_arith_ftrc" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "ftrc_s"))
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"ID_or,sh4a_fex")
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;; Single-precision FDIV/FSQRT
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;; Group: FE
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;; Latency: 20
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(define_insn_reservation "sh4a_fdiv" 20
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "fdiv"))
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"ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex")
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;; Double Precision floating point computation
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;; (FCNVDS, FCNVSD, FLOAT, FTRC)
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;; Group: FE
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;; Latency: 3
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(define_insn_reservation "sh4a_dp_float" 3
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "dfp_conv"))
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"ID_or,sh4a_fex")
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;; Double-precision floating-point (FADD,FMUL,FSUB)
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;; Group: FE
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;; Latency: 5
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(define_insn_reservation "sh4a_fp_double_arith" 5
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "dfp_arith,dfp_mul"))
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"ID_or,sh4a_fex*3")
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;; Double precision FDIV/SQRT
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;; Group: FE
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;; Latency: 36
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(define_insn_reservation "sh4a_dp_div" 36
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "dfdiv"))
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"ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex*2")
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;; FSRRA
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;; Group: FE
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;; Latency: 5
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(define_insn_reservation "sh4a_fsrra" 5
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "fsrra"))
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"ID_or,sh4a_fex")
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;; FSCA
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;; Group: FE
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;; Latency: 7
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(define_insn_reservation "sh4a_fsca" 7
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(and (eq_attr "cpu" "sh4a")
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(eq_attr "type" "fsca"))
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"ID_or,sh4a_fex*3")
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