154 lines
5.1 KiB
Markdown
154 lines
5.1 KiB
Markdown
;; DFA-based pipeline descriptions for MIPS32 4K processor family
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;; Contributed by Nigel Stephens (nigel@mips.com)
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;; and David Ung (davidu@mips.com)
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;;
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;; References:
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;; "MIPS32 4K Processor Core Family Software User's Manual,
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;; Doc no: MD00016, Rev 1.18, Nov 15, 2004."
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;;
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;; 4Kc - pipelined multiplier and translation lookaside buffer (TLB)
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;; 4km - pipelined multiplier and block address translator (BAT)
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;; 4kp - non-pipelined multiplier and block address translator (BAT)
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;;
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "r4k_cpu, r4k_mdu")
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;; Integer execution unit.
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(define_cpu_unit "r4k_ixu_arith" "r4k_cpu")
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(define_cpu_unit "r4k_ixu_mpydiv" "r4k_mdu")
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(define_insn_reservation "r4k_int_load" 2
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "load"))
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"r4k_ixu_arith")
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(define_insn_reservation "r4k_int_prefetch" 1
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "prefetch"))
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"r4k_ixu_arith")
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(define_insn_reservation "r4k_int_store" 1
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "store"))
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"r4k_ixu_arith")
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;; 4Kc/4Km
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;; unsigned divide - 8/16/24/32-bit operand have latencies 9/17/25/33
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;; signed divide - 8/16/24/32-bit operand have latencies 10/18/26/34
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(define_insn_reservation "r4k_idiv_4kc" 34
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(and (eq_attr "cpu" "4kc")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "!DI")))
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"r4k_ixu_arith+(r4k_ixu_mpydiv*34)")
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;; 4Kp
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;; unsigned divide - 33
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;; signed divide - 33-35
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(define_insn_reservation "r4k_idiv_4kp" 35
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(and (eq_attr "cpu" "4kp")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "!DI")))
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"r4k_ixu_arith+(r4k_ixu_mpydiv*35)")
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;; 4Kc/4Km fast 32x32 multiply
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;; 16x32 is faster, but there's no way to detect this
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(define_insn_reservation "r4k_mult_4kc" 2
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(and (eq_attr "cpu" "4kc")
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(and (eq_attr "type" "imul,imadd")
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(eq_attr "mode" "SI")))
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"r4k_ixu_arith+(r4k_ixu_mpydiv*2)")
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;; 4Kc/4Km MUL has 2 cycle latency, but has the special property that it will
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;; stall the integer unit pipeline. MUL 16x16 or 32x16 forces 1 cycle stall,
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;; while MUL 32x32 forces 2 cycle stall. If next insn use the result, an
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;; additional stall is forced.
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(define_insn_reservation "r4k_mul_4kc" 4
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(and (eq_attr "cpu" "4kc")
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(and (eq_attr "type" "imul3")
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(eq_attr "mode" "SI")))
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"(r4k_ixu_arith+r4k_ixu_mpydiv)*3")
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;; 4Kp slow iterative 2-op MULT
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;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO.
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;; Repeat rate of 33 cycles.
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(define_insn_reservation "r4k_mult_4kp" 32
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(and (eq_attr "cpu" "4kp")
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(and (eq_attr "type" "imul")
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(eq_attr "mode" "SI")))
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"r4k_ixu_arith+(r4k_ixu_mpydiv*32)")
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;; 4Kp slow iterative 3-op MUL
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;; Latency of 32 cycles, but stalls the whole pipeline until complete.
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(define_insn_reservation "r4k_mul_4kp" 32
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(and (eq_attr "cpu" "4kp")
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(and (eq_attr "type" "imul3")
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(eq_attr "mode" "SI")))
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"(r4k_ixu_arith+r4k_ixu_mpydiv)*32")
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;; 4Kp slow iterative MADD
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;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO.
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;; Repeat rate of 35 cycles.
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(define_insn_reservation "r4k_madd_4kp" 34
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(and (eq_attr "cpu" "4kp")
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(and (eq_attr "type" "imadd")
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(eq_attr "mode" "SI")))
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"r4k_ixu_arith+(r4k_ixu_mpydiv*34)")
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;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
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(define_insn_reservation "r4k_int_mthilo" 1
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "mthilo"))
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"r4k_ixu_arith+r4k_ixu_mpydiv")
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;; Move from HI/LO -> integer operation has a 2 cycle latency.
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(define_insn_reservation "r4k_int_mfhilo" 2
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "mfhilo"))
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"r4k_ixu_arith+r4k_ixu_mpydiv")
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;; All other integer insns.
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(define_insn_reservation "r4k_int_alu" 1
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "arith,condmove,const,logical,move,nop,shift,signext,slt"))
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"r4k_ixu_arith")
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(define_insn_reservation "r4k_int_branch" 1
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "branch"))
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"r4k_ixu_arith")
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(define_insn_reservation "r4k_int_jump_4k" 1
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "jump,call"))
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"r4k_ixu_arith")
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;; mfcx/mtcx - non FPU
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;; (Disabled until we add cop0 support)
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;; (define_insn_reservation "r4k_int_cop" 2
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;; (and (eq_attr "cpu" "4kc,4kp")
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;; (eq_attr "type" "cop0"))
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;; "r4k_ixu_arith")
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;; Unknown or multi - single issue
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(define_insn_reservation "r4k_unknown" 1
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(and (eq_attr "cpu" "4kc,4kp")
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(eq_attr "type" "unknown,multi"))
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"r4k_ixu_arith+r4k_ixu_mpydiv")
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