240 lines
8.2 KiB
Markdown
240 lines
8.2 KiB
Markdown
;; GCC machine description for i386 synchronization instructions.
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;; Copyright (C) 2005, 2006, 2007, 2008, 2009
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_mode_iterator CASMODE
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[QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
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(TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
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(define_mode_iterator DCASMODE
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[(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
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(TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
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(define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
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(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
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(define_expand "memory_barrier"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
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""
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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if (!(TARGET_64BIT || TARGET_SSE2))
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{
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emit_insn (gen_memory_barrier_nosse (operands[0]));
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DONE;
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}
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})
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(define_insn "memory_barrier_nosse"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
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(clobber (reg:CC FLAGS_REG))]
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"!(TARGET_64BIT || TARGET_SSE2)"
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"lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
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[(set_attr "memory" "unknown")])
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;; ??? It would be possible to use cmpxchg8b on pentium for DImode
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;; changes. It's complicated because the insn uses ecx:ebx as the
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;; new value; note that the registers are reversed from the order
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;; that they'd be in with (reg:DI 2 ecx). Similarly for TImode
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;; data in 64-bit mode.
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(define_expand "sync_compare_and_swap<mode>"
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[(parallel
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[(set (match_operand:CASMODE 0 "register_operand" "")
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(match_operand:CASMODE 1 "memory_operand" ""))
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(set (match_dup 1)
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(unspec_volatile:CASMODE
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[(match_dup 1)
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(match_operand:CASMODE 2 "register_operand" "")
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(match_operand:CASMODE 3 "register_operand" "")]
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UNSPECV_CMPXCHG))
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(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(unspec_volatile:CASMODE
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
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(match_dup 2)))])]
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"TARGET_CMPXCHG"
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{
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if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode)
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{
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enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode;
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rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0);
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rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode,
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GET_MODE_SIZE (hmode));
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low = force_reg (hmode, low);
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high = force_reg (hmode, high);
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if (<MODE>mode == DImode)
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{
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if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode))
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operands[1] = replace_equiv_address (operands[1],
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force_reg (Pmode,
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XEXP (operands[1],
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0)));
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emit_insn (gen_sync_double_compare_and_swapdi
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(operands[0], operands[1], operands[2], low, high));
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}
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else if (<MODE>mode == TImode)
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emit_insn (gen_sync_double_compare_and_swapti
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(operands[0], operands[1], operands[2], low, high));
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else
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gcc_unreachable ();
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DONE;
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}
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})
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(define_insn "*sync_compare_and_swap<mode>"
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[(set (match_operand:SWI 0 "register_operand" "=a")
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(match_operand:SWI 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(unspec_volatile:SWI
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[(match_dup 1)
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(match_operand:SWI 2 "register_operand" "a")
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(match_operand:SWI 3 "register_operand" "<r>")]
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UNSPECV_CMPXCHG))
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(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(unspec_volatile:SWI
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
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(match_dup 2)))]
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"TARGET_CMPXCHG"
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"lock{%;| }cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}")
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(define_insn "sync_double_compare_and_swap<mode>"
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[(set (match_operand:DCASMODE 0 "register_operand" "=A")
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(match_operand:DCASMODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(unspec_volatile:DCASMODE
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[(match_dup 1)
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(match_operand:DCASMODE 2 "register_operand" "A")
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(match_operand:<DCASHMODE> 3 "register_operand" "b")
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(match_operand:<DCASHMODE> 4 "register_operand" "c")]
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UNSPECV_CMPXCHG))
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(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(unspec_volatile:DCASMODE
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[(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
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UNSPECV_CMPXCHG)
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(match_dup 2)))]
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""
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"lock{%;| }cmpxchg<doublemodesuffix>b\t%1")
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;; Theoretically we'd like to use constraint "r" (any reg) for operand
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;; 3, but that includes ecx. If operand 3 and 4 are the same (like when
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;; the input is -1LL) GCC might chose to allocate operand 3 to ecx, like
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;; operand 4. This breaks, as the xchg will move the PIC register contents
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;; to %ecx then --> boom. Operands 3 and 4 really need to be different
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;; registers, which in this case means operand 3 must not be ecx.
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;; Instead of playing tricks with fake early clobbers or the like we
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;; just enumerate all regs possible here, which (as this is !TARGET_64BIT)
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;; are just esi and edi.
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(define_insn "*sync_double_compare_and_swapdi_pic"
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[(set (match_operand:DI 0 "register_operand" "=A")
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(match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m"))
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(set (match_dup 1)
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(unspec_volatile:DI
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[(match_dup 1)
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(match_operand:DI 2 "register_operand" "A")
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(match_operand:SI 3 "register_operand" "SD")
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(match_operand:SI 4 "register_operand" "c")]
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UNSPECV_CMPXCHG))
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(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(unspec_volatile:DI
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[(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
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UNSPECV_CMPXCHG)
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(match_dup 2)))]
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"!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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"xchg{l}\t%%ebx, %3\;lock{%;| }cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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(define_insn "sync_old_add<mode>"
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[(set (match_operand:SWI 0 "register_operand" "=<r>")
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(unspec_volatile:SWI
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[(match_operand:SWI 1 "memory_operand" "+m")] UNSPECV_XCHG))
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(set (match_dup 1)
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(plus:SWI (match_dup 1)
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(match_operand:SWI 2 "register_operand" "0")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_XADD"
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"lock{%;| }xadd{<imodesuffix>}\t{%0, %1|%1, %0}")
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;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
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(define_insn "sync_lock_test_and_set<mode>"
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[(set (match_operand:SWI 0 "register_operand" "=<r>")
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(unspec_volatile:SWI
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[(match_operand:SWI 1 "memory_operand" "+m")] UNSPECV_XCHG))
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(set (match_dup 1)
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(match_operand:SWI 2 "register_operand" "0"))]
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""
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"xchg{<imodesuffix>}\t{%1, %0|%0, %1}")
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(define_insn "sync_add<mode>"
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[(set (match_operand:SWI 0 "memory_operand" "+m")
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(unspec_volatile:SWI
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[(plus:SWI (match_dup 0)
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(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))]
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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{
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if (TARGET_USE_INCDEC)
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{
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if (operands[1] == const1_rtx)
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return "lock{%;| }inc{<imodesuffix>}\t%0";
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if (operands[1] == constm1_rtx)
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return "lock{%;| }dec{<imodesuffix>}\t%0";
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}
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if (x86_maybe_negate_const_int (&operands[1], <MODE>mode))
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return "lock{%;| }sub{<imodesuffix>}\t{%1, %0|%0, %1}";
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return "lock{%;| }add{<imodesuffix>}\t{%1, %0|%0, %1}";
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})
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(define_insn "sync_sub<mode>"
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[(set (match_operand:SWI 0 "memory_operand" "+m")
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(unspec_volatile:SWI
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[(minus:SWI (match_dup 0)
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(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))]
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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{
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if (TARGET_USE_INCDEC)
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{
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if (operands[1] == const1_rtx)
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return "lock{%;| }dec{<imodesuffix>}\t%0";
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if (operands[1] == constm1_rtx)
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return "lock{%;| }inc{<imodesuffix>}\t%0";
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}
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return "lock{%;| }sub{<imodesuffix>}\t{%1, %0|%0, %1}";
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})
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(define_insn "sync_<code><mode>"
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[(set (match_operand:SWI 0 "memory_operand" "+m")
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(unspec_volatile:SWI
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[(any_logic:SWI (match_dup 0)
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(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))]
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock{%;| }<logic>{<imodesuffix>}\t{%1, %0|%0, %1}")
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