277 lines
11 KiB
Markdown
277 lines
11 KiB
Markdown
;; ARM Cortex-A8 scheduling description.
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;; Copyright (C) 2007 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "cortex_a8")
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;; Only one load/store instruction can be issued per cycle
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;; (although reservation of this unit is only required for single
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;; loads and stores -- see below).
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(define_cpu_unit "cortex_a8_issue_ls" "cortex_a8")
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;; Only one branch instruction can be issued per cycle.
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(define_cpu_unit "cortex_a8_issue_branch" "cortex_a8")
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;; The two ALU pipelines.
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(define_cpu_unit "cortex_a8_alu0" "cortex_a8")
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(define_cpu_unit "cortex_a8_alu1" "cortex_a8")
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;; The usual flow of an instruction through the pipelines.
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(define_reservation "cortex_a8_default"
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"cortex_a8_alu0|cortex_a8_alu1")
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;; The flow of a branch instruction through the pipelines.
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(define_reservation "cortex_a8_branch"
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"(cortex_a8_alu0+cortex_a8_issue_branch)|\
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(cortex_a8_alu1+cortex_a8_issue_branch)")
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;; The flow of a load or store instruction through the pipeline in
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;; the case where that instruction consists of only one micro-op...
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(define_reservation "cortex_a8_load_store_1"
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"(cortex_a8_alu0+cortex_a8_issue_ls)|\
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(cortex_a8_alu1+cortex_a8_issue_ls)")
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;; ...and in the case of two micro-ops. We don't need to reserve
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;; cortex_a8_issue_ls here because dual issue is altogether forbidden
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;; during the issue cycle of the first micro-op. (Instead of modelling
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;; a separate issue unit, we instead reserve alu0 and alu1 to
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;; prevent any other instructions from being issued upon that first cycle.)
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;; Even though the load/store pipeline is usually available in either
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;; ALU pipe, multi-cycle instructions always issue in pipeline 0. This
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;; reservation is therefore the same as cortex_a8_multiply_2 below.
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(define_reservation "cortex_a8_load_store_2"
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"cortex_a8_alu0+cortex_a8_alu1,\
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cortex_a8_alu0")
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;; The flow of a single-cycle multiplication.
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(define_reservation "cortex_a8_multiply"
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"cortex_a8_alu0")
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;; The flow of a multiplication instruction that gets decomposed into
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;; two micro-ops. The two micro-ops will be issued to pipeline 0 on
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;; successive cycles. Dual issue cannot happen at the same time as the
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;; first of the micro-ops.
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(define_reservation "cortex_a8_multiply_2"
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"cortex_a8_alu0+cortex_a8_alu1,\
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cortex_a8_alu0")
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;; Similarly, the flow of a multiplication instruction that gets
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;; decomposed into three micro-ops. Dual issue cannot occur except on
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;; the cycle upon which the third micro-op is issued.
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(define_reservation "cortex_a8_multiply_3"
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"cortex_a8_alu0+cortex_a8_alu1,\
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cortex_a8_alu0+cortex_a8_alu1,\
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cortex_a8_alu0")
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;; The model given here assumes that all instructions are unconditional.
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;; Data processing instructions, but not move instructions.
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;; We include CLZ with these since it has the same execution pattern
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;; (source read in E2 and destination available at the end of that cycle).
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(define_insn_reservation "cortex_a8_alu" 2
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(and (eq_attr "tune" "cortexa8")
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(ior (and (eq_attr "type" "alu")
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(not (eq_attr "insn" "mov,mvn")))
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(eq_attr "insn" "clz")))
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"cortex_a8_default")
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(define_insn_reservation "cortex_a8_alu_shift" 2
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(and (eq_attr "tune" "cortexa8")
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(and (eq_attr "type" "alu_shift")
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(not (eq_attr "insn" "mov,mvn"))))
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"cortex_a8_default")
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(define_insn_reservation "cortex_a8_alu_shift_reg" 2
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(and (eq_attr "tune" "cortexa8")
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(and (eq_attr "type" "alu_shift_reg")
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(not (eq_attr "insn" "mov,mvn"))))
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"cortex_a8_default")
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;; Move instructions.
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(define_insn_reservation "cortex_a8_mov" 1
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(and (eq_attr "tune" "cortexa8")
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(and (eq_attr "type" "alu,alu_shift,alu_shift_reg")
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(eq_attr "insn" "mov,mvn")))
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"cortex_a8_default")
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;; Exceptions to the default latencies for data processing instructions.
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;; A move followed by an ALU instruction with no early dep.
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;; (Such a pair can be issued in parallel, hence latency zero.)
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(define_bypass 0 "cortex_a8_mov" "cortex_a8_alu")
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(define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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;; An ALU instruction followed by an ALU instruction with no early dep.
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(define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
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"cortex_a8_alu")
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(define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
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"cortex_a8_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
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"cortex_a8_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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;; Multiplication instructions. These are categorized according to their
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;; reservation behavior and the need below to distinguish certain
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;; varieties for bypasses. Results are available at the E5 stage
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;; (but some of these are multi-cycle instructions which explains the
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;; latencies below).
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(define_insn_reservation "cortex_a8_mul" 6
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "insn" "mul,smulxy,smmul"))
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"cortex_a8_multiply_2")
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(define_insn_reservation "cortex_a8_mla" 6
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "insn" "mla,smlaxy,smlawy,smmla,smlad,smlsd"))
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"cortex_a8_multiply_2")
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(define_insn_reservation "cortex_a8_mull" 7
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "insn" "smull,umull,smlal,umlal,umaal,smlalxy"))
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"cortex_a8_multiply_3")
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(define_insn_reservation "cortex_a8_smulwy" 5
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "insn" "smulwy,smuad,smusd"))
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"cortex_a8_multiply")
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;; smlald and smlsld are multiply-accumulate instructions but do not
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;; received bypassed data from other multiplication results; thus, they
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;; cannot go in cortex_a8_mla above. (See below for bypass details.)
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(define_insn_reservation "cortex_a8_smlald" 6
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "insn" "smlald,smlsld"))
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"cortex_a8_multiply_2")
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;; A multiply with a single-register result or an MLA, followed by an
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;; MLA with an accumulator dependency, has its result forwarded so two
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;; such instructions can issue back-to-back.
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(define_bypass 1 "cortex_a8_mul,cortex_a8_mla,cortex_a8_smulwy"
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"cortex_a8_mla"
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"arm_mac_accumulator_is_mul_result")
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;; A multiply followed by an ALU instruction needing the multiply
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;; result only at E2 has lower latency than one needing it at E1.
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(define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
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cortex_a8_smulwy,cortex_a8_smlald"
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"cortex_a8_alu")
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(define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
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cortex_a8_smulwy,cortex_a8_smlald"
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"cortex_a8_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
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cortex_a8_smulwy,cortex_a8_smlald"
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"cortex_a8_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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;; Load instructions.
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;; The presence of any register writeback is ignored here.
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;; A load result has latency 3 unless the dependent instruction has
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;; no early dep, in which case it is only latency two.
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;; We assume 64-bit alignment for doubleword loads.
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(define_insn_reservation "cortex_a8_load1_2" 3
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "type" "load1,load2,load_byte"))
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"cortex_a8_load_store_1")
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(define_bypass 2 "cortex_a8_load1_2"
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"cortex_a8_alu")
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(define_bypass 2 "cortex_a8_load1_2"
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"cortex_a8_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 2 "cortex_a8_load1_2"
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"cortex_a8_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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;; We do not currently model the fact that loads with scaled register
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;; offsets that are not LSL #2 have an extra cycle latency (they issue
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;; as two micro-ops).
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;; A load multiple of three registers is usually issued as two micro-ops.
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;; The first register will be available at E3 of the first iteration,
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;; the second at E3 of the second iteration, and the third at E4 of
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;; the second iteration. A load multiple of four registers is usually
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;; issued as two micro-ops.
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(define_insn_reservation "cortex_a8_load3_4" 5
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "type" "load3,load4"))
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"cortex_a8_load_store_2")
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(define_bypass 4 "cortex_a8_load3_4"
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"cortex_a8_alu")
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(define_bypass 4 "cortex_a8_load3_4"
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"cortex_a8_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 4 "cortex_a8_load3_4"
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"cortex_a8_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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;; Store instructions.
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;; Writeback is again ignored.
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(define_insn_reservation "cortex_a8_store1_2" 0
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "type" "store1,store2"))
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"cortex_a8_load_store_1")
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(define_insn_reservation "cortex_a8_store3_4" 0
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "type" "store3,store4"))
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"cortex_a8_load_store_2")
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;; An ALU instruction acting as a producer for a store instruction
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;; that only uses the result as the value to be stored (as opposed to
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;; using it to calculate the address) has latency zero; the store
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;; reads the value to be stored at the start of E3 and the ALU insn
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;; writes it at the end of E2. Move instructions actually produce the
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;; result at the end of E1, but since we don't have delay slots, the
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;; scheduling behavior will be the same.
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(define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\
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cortex_a8_alu_shift_reg,cortex_a8_mov"
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"cortex_a8_store1_2,cortex_a8_store3_4"
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"arm_no_early_store_addr_dep")
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;; Branch instructions
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(define_insn_reservation "cortex_a8_branch" 0
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "type" "branch"))
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"cortex_a8_branch")
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;; Call latencies are not predictable. A semi-arbitrary very large
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;; number is used as "positive infinity" so that everything should be
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;; finished by the time of return.
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(define_insn_reservation "cortex_a8_call" 32
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(and (eq_attr "tune" "cortexa8")
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(eq_attr "type" "call"))
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"cortex_a8_issue_branch")
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;; NEON (including VFP) instructions.
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(include "cortex-a8-neon.md")
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