162 lines
5.3 KiB
Markdown
162 lines
5.3 KiB
Markdown
;; Scheduling description for Alpha EV4.
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;; Copyright (C) 2002, 2004, 2005, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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; On EV4 there are two classes of resources to consider: resources needed
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; to issue, and resources needed to execute. IBUS[01] are in the first
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; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
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; (There are a few other register-like resources, but ...)
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(define_automaton "ev4_0,ev4_1,ev4_2")
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(define_cpu_unit "ev4_ib0,ev4_ib1,ev4_abox,ev4_bbox" "ev4_0")
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(define_cpu_unit "ev4_ebox,ev4_imul" "ev4_1")
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(define_cpu_unit "ev4_fbox,ev4_fdiv" "ev4_2")
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(define_reservation "ev4_ib01" "ev4_ib0|ev4_ib1")
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; Assume type "multi" single issues.
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(define_insn_reservation "ev4_multi" 1
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "multi"))
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"ev4_ib0+ev4_ib1")
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; Loads from L0 completes in three cycles. adjust_cost still factors
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; in user-specified memory latency, so return 1 here.
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(define_insn_reservation "ev4_ld" 1
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "ild,fld,ldsym,ld_l"))
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"ev4_ib01+ev4_abox")
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; Stores can issue before the data (but not address) is ready.
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(define_insn_reservation "ev4_ist" 1
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "ist"))
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"ev4_ib1+ev4_abox")
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; ??? Separate from ev4_ist because store_data_bypass_p can't handle
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; the patterns with multiple sets, like store-conditional.
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(define_insn_reservation "ev4_ist_c" 1
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "st_c"))
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"ev4_ib1+ev4_abox")
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(define_insn_reservation "ev4_fst" 1
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "fst"))
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"ev4_ib0+ev4_abox")
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; Memory barrier blocks ABOX insns until it's acknowledged by the external
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; memory bus. This may be *quite* slow. Setting this to 4 cycles gets
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; about all the benefit without making the DFA too large.
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(define_insn_reservation "ev4_mb" 4
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "mb"))
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"ev4_ib1+ev4_abox,ev4_abox*3")
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; Branches have no delay cost, but do tie up the unit for two cycles.
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(define_insn_reservation "ev4_ibr" 2
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "ibr,jsr"))
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"ev4_ib1+ev4_bbox,ev4_bbox")
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(define_insn_reservation "ev4_callpal" 2
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "callpal"))
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"ev4_ib1+ev4_bbox,ev4_bbox")
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(define_insn_reservation "ev4_fbr" 2
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "fbr"))
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"ev4_ib0+ev4_bbox,ev4_bbox")
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; Arithmetic insns are normally have their results available after
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; two cycles. There are a number of exceptions.
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(define_insn_reservation "ev4_iaddlog" 2
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "iadd,ilog"))
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"ev4_ib0+ev4_ebox")
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(define_bypass 1
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"ev4_iaddlog"
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"ev4_ibr,ev4_iaddlog,ev4_shiftcm,ev4_icmp,ev4_imulsi,ev4_imuldi")
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(define_insn_reservation "ev4_shiftcm" 2
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "shift,icmov"))
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"ev4_ib0+ev4_ebox")
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(define_insn_reservation "ev4_icmp" 2
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "icmp"))
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"ev4_ib0+ev4_ebox")
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(define_bypass 1 "ev4_icmp" "ev4_ibr")
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(define_bypass 0
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"ev4_iaddlog,ev4_shiftcm,ev4_icmp"
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"ev4_ist"
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"store_data_bypass_p")
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; Multiplies use a non-pipelined imul unit. Also, "no [ebox] insn can
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; be issued exactly three cycles before an integer multiply completes".
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(define_insn_reservation "ev4_imulsi" 21
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(and (eq_attr "tune" "ev4")
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(and (eq_attr "type" "imul")
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(eq_attr "opsize" "si")))
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"ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox")
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(define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p")
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(define_insn_reservation "ev4_imuldi" 23
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(and (eq_attr "tune" "ev4")
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(and (eq_attr "type" "imul")
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(eq_attr "opsize" "!si")))
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"ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox")
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(define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p")
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; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in.
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(define_insn_reservation "ev4_fpop" 6
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "fadd,fmul,fcpys,fcmov"))
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"ev4_ib1+ev4_fbox")
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(define_bypass 4 "ev4_fpop" "ev4_fpop")
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; The floating point divider is not pipelined. Also, "no FPOP insn can be
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; issued exactly five or exactly six cycles before an fdiv insn completes".
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(define_insn_reservation "ev4_fdivsf" 34
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(and (eq_attr "tune" "ev4")
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(and (eq_attr "type" "fdiv")
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(eq_attr "opsize" "si")))
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"ev4_ib1+ev4_fdiv,ev4_fdiv*28,ev4_fdiv+ev4_fbox,ev4_fbox")
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(define_insn_reservation "ev4_fdivdf" 63
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(and (eq_attr "tune" "ev4")
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(and (eq_attr "type" "fdiv")
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(eq_attr "opsize" "di")))
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"ev4_ib1+ev4_fdiv,ev4_fdiv*57,ev4_fdiv+ev4_fbox,ev4_fbox")
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; Traps don't consume or produce data.
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(define_insn_reservation "ev4_misc" 1
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "misc"))
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"ev4_ib1")
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