190 lines
6.6 KiB
Markdown
190 lines
6.6 KiB
Markdown
;; Scheduling description for UltraSPARC-III.
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;; Copyright (C) 2002, 2004, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; UltraSPARC-III is a quad-issue processor.
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;;
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;; It is also a much simpler beast than Ultra-I/II, no silly
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;; slotting rules and both integer units are fully symmetric.
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;; It does still have single-issue instructions though.
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(define_automaton "ultrasparc3_0,ultrasparc3_1")
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(define_cpu_unit "us3_ms,us3_br,us3_fpm" "ultrasparc3_0")
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(define_cpu_unit "us3_a0,us3_a1,us3_slot0,\
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us3_slot1,us3_slot2,us3_slot3,us3_fpa" "ultrasparc3_1")
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(define_cpu_unit "us3_load_writeback" "ultrasparc3_1")
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(define_reservation "us3_slotany" "(us3_slot0 | us3_slot1 | us3_slot2 | us3_slot3)")
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(define_reservation "us3_single_issue" "us3_slot0 + us3_slot1 + us3_slot2 + us3_slot3")
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(define_reservation "us3_ax" "(us3_a0 | us3_a1)")
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(define_insn_reservation "us3_single" 1
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "multi,savew,flushw,iflush,trap"))
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"us3_single_issue")
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(define_insn_reservation "us3_integer" 1
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "ialu,shift,compare"))
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"us3_ax + us3_slotany")
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(define_insn_reservation "us3_ialuX" 5
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "ialu,shift,compare"))
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"us3_single_issue*4, nothing")
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(define_insn_reservation "us3_cmove" 2
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "cmove"))
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"us3_ms + us3_br + us3_slotany, nothing")
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;; ??? Not entirely accurate.
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;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe
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;; ??? is needed, and the instruction group is broken right after
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;; ??? the imul. Then 'helper' instructions are generated to perform
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;; ??? each further stage of the multiplication, each such 'helper' is
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;; ??? single group. So, the reservation aspect is represented accurately
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;; ??? here, but the variable cycles are not.
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;; ??? Currently I have no idea how to determine the variability, but once
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;; ??? known we can simply add a define_bypass or similar to model it.
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(define_insn_reservation "us3_imul" 7
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "imul"))
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"us3_ms + us3_slotany, us3_single_issue*4, nothing*2")
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(define_insn_reservation "us3_idiv" 72
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "idiv"))
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"us3_ms + us3_slotany, us3_single_issue*69, nothing*2")
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;; UltraSPARC-III has a similar load delay as UltraSPARC-I/II except
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;; that all loads except 32-bit/64-bit unsigned loads take the extra
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;; delay for sign/zero extension.
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(define_insn_reservation "us3_2cycle_load" 2
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(and (eq_attr "cpu" "ultrasparc3")
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(and (eq_attr "type" "load,fpload")
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(eq_attr "us3load_type" "2cycle")))
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"us3_ms + us3_slotany, us3_load_writeback")
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(define_insn_reservation "us3_load_delayed" 3
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(and (eq_attr "cpu" "ultrasparc3")
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(and (eq_attr "type" "load,sload")
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(eq_attr "us3load_type" "3cycle")))
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"us3_ms + us3_slotany, nothing, us3_load_writeback")
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(define_insn_reservation "us3_store" 1
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "store,fpstore"))
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"us3_ms + us3_slotany")
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(define_insn_reservation "us3_branch" 1
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "branch"))
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"us3_br + us3_slotany")
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(define_insn_reservation "us3_call_jmpl" 1
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch"))
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"us3_br + us3_ms + us3_slotany")
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(define_insn_reservation "us3_fmov" 3
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpmove"))
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"us3_fpa + us3_slotany, nothing*2")
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(define_insn_reservation "us3_fcmov" 3
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpcmove"))
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"us3_fpa + us3_br + us3_slotany, nothing*2")
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(define_insn_reservation "us3_fcrmov" 3
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpcrmove"))
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"us3_fpa + us3_ms + us3_slotany, nothing*2")
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(define_insn_reservation "us3_faddsub" 4
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fp"))
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"us3_fpa + us3_slotany, nothing*3")
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(define_insn_reservation "us3_fpcmp" 5
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpcmp"))
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"us3_fpa + us3_slotany, nothing*4")
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(define_insn_reservation "us3_fmult" 4
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpmul"))
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"us3_fpm + us3_slotany, nothing*3")
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(define_insn_reservation "us3_fdivs" 17
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpdivs"))
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"(us3_fpm + us3_slotany), us3_fpm*14, nothing*2")
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(define_insn_reservation "us3_fsqrts" 20
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpsqrts"))
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"(us3_fpm + us3_slotany), us3_fpm*17, nothing*2")
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(define_insn_reservation "us3_fdivd" 20
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpdivd"))
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"(us3_fpm + us3_slotany), us3_fpm*17, nothing*2")
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(define_insn_reservation "us3_fsqrtd" 29
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fpsqrtd"))
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"(us3_fpm + us3_slotany), us3_fpm*26, nothing*2")
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;; Any store may multi issue with the insn creating the source
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;; data as long as that creating insn is not an FPU div/sqrt.
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;; We need a special guard function because this bypass does
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;; not apply to the address inputs of the store.
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(define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store"
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"store_data_bypass_p")
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;; An integer branch may execute in the same cycle as the compare
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;; creating the condition codes.
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(define_bypass 0 "us3_integer" "us3_branch")
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;; If FMOVfcc is user of FPCMP, latency is only 1 cycle.
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(define_bypass 1 "us3_fpcmp" "us3_fcmov")
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;; VIS scheduling
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(define_insn_reservation "us3_fga"
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3
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fga"))
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"us3_fpa + us3_slotany, nothing*2")
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(define_insn_reservation "us3_fgm"
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4
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp"))
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"us3_fpm + us3_slotany, nothing*3")
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(define_insn_reservation "us3_pdist"
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4
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(and (eq_attr "cpu" "ultrasparc3")
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(eq_attr "type" "fgm_pdist"))
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"us3_fpm + us3_slotany, nothing*3")
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(define_bypass 1 "us3_pdist" "us3_pdist")
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