288 lines
10 KiB
Markdown
288 lines
10 KiB
Markdown
;; DFA scheduling description for ST40-300.
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;; Copyright (C) 2004, 2006, 2007 Free Software Foundation, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Load and store instructions save a cycle if they are aligned on a
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;; four byte boundary. Using a function unit for stores encourages
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;; gcc to separate load and store instructions by one instruction,
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;; which makes it more likely that the linker will be able to word
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;; align them when relaxing.
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;; The following description models the ST40-300 pipeline using the DFA based
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;; scheduler.
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;; Two automata are defined to reduce number of states
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;; which a single large automaton will have. (Factoring)
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(define_automaton "sh4_300_inst_pipeline,sh4_300_fpu_pipe")
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;; This unit is basically the decode unit of the processor.
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;; Since SH4 is a dual issue machine,it is as if there are two
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;; units so that any insn can be processed by either one
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;; of the decoding unit.
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(define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline")
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;; The floating point units.
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(define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe")
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;; integer multiplier unit
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(define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline")
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;; LS unit
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(define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline")
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;; The address calculator used for branch instructions.
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;; This will be reserved after "issue" of branch instructions
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;; and this is to make sure that no two branch instructions
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;; can be issued in parallel.
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(define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline")
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;; ----------------------------------------------------
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;; This reservation is to simplify the dual issue description.
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(define_reservation "sh4_300_issue" "sh4_300_pipe_01|sh4_300_pipe_02")
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(define_reservation "all" "sh4_300_pipe_01+sh4_300_pipe_02")
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;;(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
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;; MOV RM,RN / MOV #imm8,RN / STS PR,RN
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(define_insn_reservation "sh4_300_mov" 0
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "move,movi8,prget"))
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"sh4_300_issue")
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;; Fixed STS from MACL / MACH
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(define_insn_reservation "sh4_300_mac_gp" 0
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "mac_gp"))
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"sh4_300_issue+sh4_300_mul")
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;; Fixed LDS to MACL / MACH
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(define_insn_reservation "sh4_300_gp_mac" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "gp_mac"))
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"sh4_300_issue+sh4_300_mul")
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;; Instructions without specific resource requirements with latency 1.
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(define_insn_reservation "sh4_300_simple_arith" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "mt_group,arith,dyn_shift,prset"))
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"sh4_300_issue")
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;; Load and store instructions have no alignment peculiarities for the ST40-300,
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;; but they use the load-store unit, which they share with the fmove type
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;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
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;; Loads have a latency of three.
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;; Load Store instructions.
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(define_insn_reservation "sh4_300_load" 3
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "load,pcload,load_si,pcload_si,pload"))
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"sh4_300_issue+sh4_300_ls")
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(define_insn_reservation "sh4_300_mac_load" 3
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "mem_mac"))
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"sh4_300_issue+sh4_300_ls+sh4_300_mul")
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(define_insn_reservation "sh4_300_fload" 4
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "fload,pcfload"))
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"sh4_300_issue+sh4_300_ls+sh4_300_fpt")
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;; sh_adjust_cost describes the reduced latency of the feeding insns of a store.
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;; The latency of an auto-increment register is 1; the latency of the memory
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;; output is not actually considered here anyway.
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(define_insn_reservation "sh4_300_store" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "store,pstore"))
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"sh4_300_issue+sh4_300_ls")
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(define_insn_reservation "sh4_300_fstore" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "fstore"))
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"sh4_300_issue+sh4_300_ls+sh4_300_fpt")
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;; Fixed STS.L from MACL / MACH
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(define_insn_reservation "sh4_300_mac_store" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "mac_mem"))
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"sh4_300_issue+sh4_300_mul+sh4_300_ls")
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(define_insn_reservation "sh4_300_gp_fpul" 2
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "gp_fpul"))
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"sh4_300_issue+sh4_300_fpt")
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(define_insn_reservation "sh4_300_fpul_gp" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "fpul_gp"))
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"sh4_300_issue+sh4_300_fpt")
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;; Branch (BF,BF/S,BT,BT/S,BRA)
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;; Branch Far (JMP,RTS,BRAF)
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;; Group: BR
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;; When displacement is 0 for BF / BT, we have effectively conditional
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;; execution of one instruction, without pipeline disruption.
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;; Otherwise, the latency depends on prediction success.
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;; We can't really do much with the latency, even if we could express it,
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;; but the pairing restrictions are useful to take into account.
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;; ??? If the branch is likely, and not paired with a preceding insn,
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;; or likely and likely not predicted, we might want to fill the delay slot.
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;; However, there appears to be no machinery to make the compiler
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;; recognize these scenarios.
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(define_insn_reservation "sh4_300_branch" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "cbranch,jump,return,jump_ind"))
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"sh4_300_issue+sh4_300_br")
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;; RTE
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(define_insn_reservation "sh4_300_return_from_exp" 9
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "rte"))
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"sh4_300_pipe_01+sh4_300_pipe_02*9")
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;; OCBP, OCBWB
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;; Group: CO
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;; Latency: 1-5
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;; Issue Rate: 1
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;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
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;; This description is likely inexact, but this pattern should not actually
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;; appear when compiling for sh4-300; we should use isbi instead.
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;; If a -mtune option is added later, we should use the icache array
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;; dispatch method instead.
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(define_insn_reservation "sh4_300_ocbwb" 3
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "cwb"))
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"all*3")
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;; JSR,BSR,BSRF
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;; Calls have a mandatory delay slot, which we'd like to fill with an insn
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;; that can be paired with the call itself.
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;; Scheduling runs before reorg, so we approximate this by saying that we
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;; want the call to be paired with a preceding insn.
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;; In most cases, the insn that loads the address of the call should have
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;; a nonzero latency (mov rn,rm doesn't make sense since we could use rn
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;; for the address then). Thus, a preceding insn that can be paired with
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;; a call should be eligible for the delay slot.
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;;
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;; calls introduce a longisch delay that is likely to flush the pipelines
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;; of the caller's instructions. Ordinary functions tend to end with a
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;; load to restore a register (in the delay slot of rts), while sfuncs
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;; tend to end with an EX or MT insn. But that is not actually relevant,
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;; since there are no instructions that contend for memory access early.
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;; We could, of course, provide exact scheduling information for specific
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;; sfuncs, if that should prove useful.
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(define_insn_reservation "sh4_300_call" 16
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "call,sfunc"))
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"sh4_300_issue+sh4_300_br,all*15")
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;; FMOV.S / FMOV.D
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(define_insn_reservation "sh4_300_fmov" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "fmove"))
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"sh4_300_issue+sh4_300_fpt")
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;; LDS to FPSCR
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(define_insn_reservation "sh4_300_fpscr_load" 8
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "gp_fpscr"))
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"sh4_300_issue+sh4_300_fpu+sh4_300_fpt")
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;; LDS.L to FPSCR
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(define_insn_reservation "sh4_300_fpscr_load_mem" 8
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "mem_fpscr"))
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"sh4_300_issue+sh4_300_fpu+sh4_300_fpt+sh4_300_ls")
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;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
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(define_insn_reservation "multi" 2
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "smpy,dmpy"))
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"sh4_300_issue+sh4_300_mul")
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;; FPCHG, FRCHG, FSCHG
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(define_insn_reservation "fpscr_toggle" 1
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "fpscr_toggle"))
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"sh4_300_issue+sh4_300_fpu+sh4_300_fpt")
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;; FCMP/EQ, FCMP/GT
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(define_insn_reservation "fp_cmp" 3
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "fp_cmp,dfp_cmp"))
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"sh4_300_issue+sh4_300_fpu")
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;; Single precision floating point (FADD,FLOAT,FMAC,FMUL,FSUB,FTRC)
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;; Double-precision floating-point (FADD,FCNVDS,FCNVSD,FLOAT,FSUB,FTRC)
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(define_insn_reservation "fp_arith" 6
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "fp,ftrc_s,dfp_arith,dfp_conv"))
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"sh4_300_issue+sh4_300_fpu")
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;; Single Precision FDIV/SQRT
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(define_insn_reservation "fp_div" 19
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "fdiv"))
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"sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*15")
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;; Double-precision floating-point FMUL
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(define_insn_reservation "dfp_mul" 9
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "dfp_mul"))
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"sh4_300_issue+sh4_300_fpu,sh4_300_fpu*3")
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;; Double precision FDIV/SQRT
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(define_insn_reservation "dp_div" 35
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "dfdiv"))
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"sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31")
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;; ??? We don't really want these for sh4-300.
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;; this pattern itself is likely to finish in 3 cycles, but also
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;; to disrupt branch prediction for taken branches for the following
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;; condbranch.
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(define_insn_reservation "sh4_300_arith3" 5
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(and (eq_attr "pipe_model" "sh4_300")
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(eq_attr "type" "arith3"))
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"sh4_300_issue,all*4")
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;; arith3b insns without brach redirection make use of the 0-offset 0-latency
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;; branch feature, and thus schedule the same no matter if the branch is taken
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;; or not. If the branch is redirected, the taken branch might take longer,
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;; but then, we don't have to take the next branch.
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;; ??? should we suppress branch redirection for sh4-300 to improve branch
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;; target hit rates?
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(define_insn_reservation "arith3b" 2
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "arith3"))
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"issue,all")
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