251 lines
9.9 KiB
Markdown
251 lines
9.9 KiB
Markdown
;; Pipeline description for Motorola PowerPC 8540 processor.
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;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
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(define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
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;; We don't simulate general issue queue (GIC). If we have SU insn
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;; and then SU1 insn, they cannot be issued on the same cycle
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;; (although SU1 insn and then SU insn can be issued) because the SU
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;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
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;; multipass insn scheduling will find the situation and issue the SU1
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;; insn and then the SU insn.
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(define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most")
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;; We could describe completion buffers slots in combination with the
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;; retirement units and the order of completion but the result
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;; automaton would behave in the same way because we cannot describe
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;; real latency time with taking in order completion into account.
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;; Actually we could define the real latency time by querying reserved
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;; automaton units but the current scheduler uses latency time before
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;; issuing insns and making any reservations.
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;;
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;; So our description is aimed to achieve a insn schedule in which the
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;; insns would not wait in the completion buffer.
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(define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire")
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;; Branch unit:
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(define_cpu_unit "ppc8540_bu" "ppc8540_most")
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;; SU:
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(define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most")
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;; We could describe here MU subunits for float multiply, float add
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;; etc. But the result automaton would behave the same way as the
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;; described one pipeline below because MU can start only one insn
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;; per cycle. Actually we could simplify the automaton more not
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;; describing stages 1-3, the result automata would be the same.
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(define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most")
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(define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most")
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;; The following unit is used to describe non-pipelined division.
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(define_cpu_unit "ppc8540_mu_div" "ppc8540_long")
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;; Here we simplified LSU unit description not describing the stages.
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(define_cpu_unit "ppc8540_lsu" "ppc8540_most")
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;; The following units are used to make automata deterministic
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(define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most")
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(define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most")
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(define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire")
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(define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most")
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;; The following sets to make automata deterministic when option ndfa is used.
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(presence_set "present_ppc8540_decode_0" "ppc8540_decode_0")
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(presence_set "present_ppc8540_issue_0" "ppc8540_issue_0")
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(presence_set "present_ppc8540_retire_0" "ppc8540_retire_0")
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(presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0")
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;; Some useful abbreviations.
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(define_reservation "ppc8540_decode"
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"ppc8540_decode_0|ppc8540_decode_1+present_ppc8540_decode_0")
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(define_reservation "ppc8540_issue"
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"ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0")
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(define_reservation "ppc8540_retire"
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"ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0")
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(define_reservation "ppc8540_su_stage0"
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"ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0")
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;; Simple SU insns
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(define_insn_reservation "ppc8540_su" 1
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(and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
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delayed_compare,var_delayed_compare,fast_compare,\
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shift,trap,var_shift_rotate,cntlz,exts,isel")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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(define_insn_reservation "ppc8540_two" 1
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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(define_insn_reservation "ppc8540_three" 1
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Branch. Actually this latency time is not used by the scheduler.
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(define_insn_reservation "ppc8540_branch" 1
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(and (eq_attr "type" "jmpreg,branch,isync")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_bu,ppc8540_retire")
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;; Multiply
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(define_insn_reservation "ppc8540_multiply" 4
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; Divide. We use the average latency time here. We omit reserving a
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;; retire unit because of the result automata will be huge. We ignore
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;; reservation of miu_stage3 here because we use the average latency
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;; time.
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(define_insn_reservation "ppc8540_divide" 14
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*13")
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;; CR logical
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(define_insn_reservation "ppc8540_cr_logical" 1
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_bu,ppc8540_retire")
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;; Mfcr
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(define_insn_reservation "ppc8540_mfcr" 1
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Mtcrf
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(define_insn_reservation "ppc8540_mtcrf" 1
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Mtjmpr
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(define_insn_reservation "ppc8540_mtjmpr" 1
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Loads
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(define_insn_reservation "ppc8540_load" 3
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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load_l,sync")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Stores.
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(define_insn_reservation "ppc8540_store" 3
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(and (eq_attr "type" "store,store_ux,store_u,store_c")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Simple FP
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(define_insn_reservation "ppc8540_simple_float" 1
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(and (eq_attr "type" "fpsimple")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; FP
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(define_insn_reservation "ppc8540_float" 4
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; float divides. We omit reserving a retire unit and miu_stage3
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;; because of the result automata will be huge.
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(define_insn_reservation "ppc8540_float_vector_divide" 29
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(and (eq_attr "type" "vecfdiv")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*28")
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;; Brinc
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(define_insn_reservation "ppc8540_brinc" 1
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(and (eq_attr "type" "brinc")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Simple vector
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(define_insn_reservation "ppc8540_simple_vector" 1
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(and (eq_attr "type" "vecsimple")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Simple vector compare
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(define_insn_reservation "ppc8540_simple_vector_compare" 1
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(and (eq_attr "type" "veccmpsimple")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Vector compare
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(define_insn_reservation "ppc8540_vector_compare" 1
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(and (eq_attr "type" "veccmp")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; evsplatfi evsplati
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(define_insn_reservation "ppc8540_vector_perm" 1
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(and (eq_attr "type" "vecperm")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Vector float
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(define_insn_reservation "ppc8540_float_vector" 4
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(and (eq_attr "type" "vecfloat")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; Vector divides: Use the average. We omit reserving a retire unit
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;; because of the result automata will be huge. We ignore reservation
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;; of miu_stage3 here because we use the average latency time.
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(define_insn_reservation "ppc8540_vector_divide" 14
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(and (eq_attr "type" "vecdiv")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*13")
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;; Complex vector.
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(define_insn_reservation "ppc8540_complex_vector" 4
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(and (eq_attr "type" "veccomplex")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; Vector load
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(define_insn_reservation "ppc8540_vector_load" 3
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(and (eq_attr "type" "vecload")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Vector store
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(define_insn_reservation "ppc8540_vector_store" 3
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(and (eq_attr "type" "vecstore")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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