1475 lines
40 KiB
Markdown
1475 lines
40 KiB
Markdown
;;- Machine description for the pdp11 for GNU C compiler
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;; Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2004, 2005
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;; 2007, 2008 Free Software Foundation, Inc.
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;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Match CONST_DOUBLE zero for tstd/tstf.
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(define_predicate "register_or_const0_operand"
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(ior (match_operand 0 "register_operand")
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(match_test "op == CONST0_RTX (GET_MODE (op))")))
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;; HI is 16 bit
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;; QI is 8 bit
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
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;;- updates for most instructions.
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;;- Operand classes for the register allocator:
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;; Compare instructions.
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;; currently we only support df floats, which saves us quite some
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;; hassle switching the FP mode!
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;; we assume that CPU is always in long float mode, and
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;; 16 bit integer mode - currently, the prologue for main does this,
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;; but maybe we should just set up a NEW crt0 properly,
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;; -- and what about signal handling code?
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;; (we don't even let sf floats in the register file, so
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;; we only should have to worry about truncating and widening
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;; when going to memory)
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;; abort() call by g++ - must define libfunc for cmp_optab
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;; and ucmp_optab for mode SImode, because we don't have that!!!
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;; - yet since no libfunc is there, we abort ()
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;; The only thing that remains to be done then is output
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;; the floats in a way the assembler can handle it (and
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;; if you're really into it, use a PDP11 float emulation
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;; library to do floating point constant folding - but
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;; I guess you'll get reasonable results even when not
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;; doing this)
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;; the last thing to do is fix the UPDATE_CC macro to check
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;; for floating point condition codes, and set cc_status
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;; properly, also setting the CC_IN_FCCR flag.
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;; define attributes
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;; currently type is only fpu or arith or unknown, maybe branch later ?
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;; default is arith
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(define_attr "type" "unknown,arith,fp" (const_string "arith"))
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;; length default is 1 word each
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(define_attr "length" "" (const_int 1))
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;; a user's asm statement
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(define_asm_attributes
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[(set_attr "type" "unknown")
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; all bets are off how long it is - make it 256, forces long jumps
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; whenever jumping around it !!!
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(set_attr "length" "256")])
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;; define function units
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;; arithmetic - values here immediately when next insn issued
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;; or does it mean the number of cycles after this insn was issued?
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;; how do I say that fpu insns use cpu also? (pre-interaction phase)
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;(define_function_unit "cpu" 1 1 (eq_attr "type" "arith") 0 0)
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;(define_function_unit "fpu" 1 1 (eq_attr "type" "fp") 0 0)
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;; compare
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(define_insn "*cmpdf"
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[(set (cc0)
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(compare (match_operand:DF 0 "general_operand" "fR,fR,Q,Q,F")
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(match_operand:DF 1 "register_or_const0_operand" "G,a,G,a,a")))]
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"TARGET_FPU"
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"*
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{
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cc_status.flags = CC_IN_FPU;
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if (which_alternative == 0 || which_alternative == 2)
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return \"{tstd|tstf} %0, %1\;cfcc\";
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else
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return \"{cmpd|cmpf} %0, %1\;cfcc\";
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}"
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[(set_attr "length" "2,2,3,3,6")])
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(define_insn "*cmphi"
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[(set (cc0)
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(compare (match_operand:HI 0 "general_operand" "rR,rR,rR,Q,Qi,Qi")
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(match_operand:HI 1 "general_operand" "N,rR,Qi,N,rR,Qi")))]
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""
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"@
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tst %0
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cmp %0,%1
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cmp %0,%1
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tst %0
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cmp %0,%1
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cmp %0,%1"
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[(set_attr "length" "1,1,2,2,2,3")])
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(define_insn "*cmpqi"
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[(set (cc0)
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(compare (match_operand:QI 0 "general_operand" "rR,rR,rR,Q,Qi,Qi")
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(match_operand:QI 1 "general_operand" "N,rR,Qi,N,rR,Qi")))]
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""
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"@
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tstb %0
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cmpb %0,%1
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cmpb %0,%1
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tstb %0
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cmpb %0,%1
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cmpb %0,%1"
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[(set_attr "length" "1,1,2,2,2,3")])
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;; sob instruction - we need an assembler which can make this instruction
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;; valid under _all_ circumstances!
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(define_insn ""
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[(set (pc)
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(if_then_else
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(ne (plus:HI (match_operand:HI 0 "register_operand" "+r")
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(const_int -1))
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_dup 0)
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(plus:HI (match_dup 0)
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(const_int -1)))]
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"TARGET_40_PLUS"
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"*
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{
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static int labelcount = 0;
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static char buf[1000];
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if (get_attr_length (insn) == 1)
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return \"sob %0, %l1\";
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/* emulate sob */
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output_asm_insn (\"dec %0\", operands);
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sprintf (buf, \"bge LONG_SOB%d\", labelcount);
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output_asm_insn (buf, NULL);
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output_asm_insn (\"jmp %l1\", operands);
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sprintf (buf, \"LONG_SOB%d:\", labelcount++);
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output_asm_insn (buf, NULL);
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return \"\";
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}"
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[(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
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(pc))
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(const_int -256))
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(ge (minus (match_dup 0)
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(pc))
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(const_int 0)))
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(const_int 4)
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(const_int 1)))])
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;; These control RTL generation for conditional jump insns
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;; and match them for register allocation.
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(define_expand "cbranchdf4"
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[(set (cc0)
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(compare (match_operand:DF 1 "general_operand")
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(match_operand:DF 2 "general_operand")))
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(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(cc0) (const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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""
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"")
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(define_expand "cbranchhi4"
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[(set (cc0)
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(compare (match_operand:HI 1 "general_operand")
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(match_operand:HI 2 "general_operand")))
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(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(cc0) (const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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""
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"")
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(define_expand "cbranchqi4"
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[(set (cc0)
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(compare (match_operand:QI 1 "general_operand")
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(match_operand:QI 2 "general_operand")))
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(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(cc0) (const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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""
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"")
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;; problem with too short jump distance! we need an assembler which can
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;; make this valid for all jump distances!
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;; e.g. gas!
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;; these must be changed to check for CC_IN_FCCR if float is to be
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;; enabled
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(define_insn "*branch"
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[(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(cc0) (const_int 0)])
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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"* return output_jump(GET_CODE (operands[0]), 0, get_attr_length(insn));"
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[(set (attr "length") (if_then_else (ior (le (minus (match_dup 1)
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(pc))
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(const_int -128))
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(ge (minus (match_dup 1)
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(pc))
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(const_int 128)))
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(const_int 3)
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(const_int 1)))])
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;; These match inverted jump insns for register allocation.
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(define_insn "*branch_inverted"
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[(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(cc0) (const_int 0)])
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(pc)
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(label_ref (match_operand 1 "" ""))))]
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""
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"* return output_jump(GET_CODE (operands[0]), 1, get_attr_length(insn));"
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[(set (attr "length") (if_then_else (ior (le (minus (match_dup 1)
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(pc))
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(const_int -128))
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(ge (minus (match_dup 1)
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(pc))
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(const_int 128)))
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(const_int 3)
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(const_int 1)))])
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;; Move instructions
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(define_insn "movdi"
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[(set (match_operand:DI 0 "general_operand" "=g,rm,o")
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(match_operand:DI 1 "general_operand" "m,r,a"))]
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""
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"* return output_move_quad (operands);"
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;; what's the mose expensive code - say twice movsi = 16
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[(set_attr "length" "16,16,16")])
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(define_insn "movsi"
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[(set (match_operand:SI 0 "general_operand" "=r,r,r,rm,m")
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(match_operand:SI 1 "general_operand" "rN,IJ,K,m,r"))]
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""
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"* return output_move_double (operands);"
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;; what's the most expensive code ? - I think 8!
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;; we could split it up and make several sub-cases...
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[(set_attr "length" "2,3,4,8,8")])
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(define_insn "movhi"
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[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
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(match_operand:HI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
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""
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"*
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{
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if (operands[1] == const0_rtx)
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return \"clr %0\";
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return \"mov %1, %0\";
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}"
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[(set_attr "length" "1,2,2,3")])
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(define_insn "movqi"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=g")
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(match_operand:QI 1 "general_operand" "g"))]
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""
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"*
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{
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if (operands[1] == const0_rtx)
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return \"clrb %0\";
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return \"movb %1, %0\";
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}"
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[(set_attr "length" "1")])
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;; do we have to supply all these moves? e.g. to
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;; NO_LOAD_FPU_REGs ?
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(define_insn "movdf"
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[(set (match_operand:DF 0 "general_operand" "=a,fR,a,Q,m")
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(match_operand:DF 1 "general_operand" "fFR,a,Q,a,m"))]
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""
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"* if (which_alternative ==0)
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return \"ldd %1, %0\";
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else if (which_alternative == 1)
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return \"std %1, %0\";
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else
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return output_move_quad (operands); "
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;; just a guess..
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[(set_attr "length" "1,1,5,5,16")])
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(define_insn "movsf"
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[(set (match_operand:SF 0 "general_operand" "=g,r,g")
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(match_operand:SF 1 "general_operand" "r,rmF,g"))]
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"TARGET_FPU"
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"* return output_move_double (operands);"
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[(set_attr "length" "8,8,8")])
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;; maybe fiddle a bit with move_ratio, then
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;; let constraints only accept a register ...
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(define_expand "movmemhi"
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[(parallel [(set (match_operand:BLK 0 "general_operand" "=g,g")
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(match_operand:BLK 1 "general_operand" "g,g"))
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(use (match_operand:HI 2 "arith_operand" "n,&mr"))
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(use (match_operand:HI 3 "immediate_operand" "i,i"))
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(clobber (match_scratch:HI 4 "=&r,X"))
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(clobber (match_dup 5))
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(clobber (match_dup 6))
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(clobber (match_dup 2))])]
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"(TARGET_BCOPY_BUILTIN)"
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"
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{
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operands[0]
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= replace_equiv_address (operands[0],
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copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
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operands[1]
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= replace_equiv_address (operands[1],
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copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
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operands[5] = XEXP (operands[0], 0);
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operands[6] = XEXP (operands[1], 0);
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}")
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(define_insn "" ; "movmemhi"
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[(set (mem:BLK (match_operand:HI 0 "general_operand" "=r,r"))
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(mem:BLK (match_operand:HI 1 "general_operand" "r,r")))
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(use (match_operand:HI 2 "arith_operand" "n,&r"))
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(use (match_operand:HI 3 "immediate_operand" "i,i"))
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(clobber (match_scratch:HI 4 "=&r,X"))
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(clobber (match_dup 0))
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(clobber (match_dup 1))
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(clobber (match_dup 2))]
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"(TARGET_BCOPY_BUILTIN)"
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"* return output_block_move (operands);"
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;;; just a guess
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[(set_attr "length" "40")])
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;;- truncation instructions
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(define_insn "truncdfsf2"
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[(set (match_operand:SF 0 "general_operand" "=r,R,Q")
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(float_truncate:SF (match_operand:DF 1 "register_operand" "a,a,a")))]
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"TARGET_FPU"
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"* if (which_alternative ==0)
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{
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output_asm_insn(\"{stcdf|movfo} %1, -(sp)\", operands);
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output_asm_insn(\"mov (sp)+, %0\", operands);
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operands[0] = gen_rtx_REG (HImode, REGNO (operands[0])+1);
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output_asm_insn(\"mov (sp)+, %0\", operands);
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return \"\";
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}
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else if (which_alternative == 1)
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return \"{stcdf|movfo} %1, %0\";
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else
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return \"{stcdf|movfo} %1, %0\";
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"
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[(set_attr "length" "3,1,2")])
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(define_expand "truncsihi2"
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[(set (match_operand:HI 0 "general_operand" "=g")
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(subreg:HI
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(match_operand:SI 1 "general_operand" "or")
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0))]
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""
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"")
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;;- zero extension instructions
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(define_insn "zero_extendqihi2"
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[(set (match_operand:HI 0 "general_operand" "=r")
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(zero_extend:HI (match_operand:QI 1 "general_operand" "0")))]
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""
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"bic $0177400, %0"
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[(set_attr "length" "2")])
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(define_expand "zero_extendhisi2"
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[(set (subreg:HI
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(match_dup 0)
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2)
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(match_operand:HI 1 "register_operand" "r"))
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(set (subreg:HI
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(match_operand:SI 0 "register_operand" "=r")
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0)
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(const_int 0))]
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""
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"/* operands[1] = make_safe_from (operands[1], operands[0]); */")
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||
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;;- sign extension instructions
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(define_insn "extendsfdf2"
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[(set (match_operand:DF 0 "register_operand" "=a,a,a")
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(float_extend:DF (match_operand:SF 1 "general_operand" "r,R,Q")))]
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"TARGET_FPU"
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||
"@
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mov %1, -(sp)\;{ldcfd|movof} (sp)+,%0
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{ldcfd|movof} %1, %0
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{ldcfd|movof} %1, %0"
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[(set_attr "length" "2,1,2")])
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||
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;; does movb sign extend in register-to-register move?
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(define_insn "extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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(sign_extend:HI (match_operand:QI 1 "general_operand" "rR,Q")))]
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""
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"movb %1, %0"
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[(set_attr "length" "1,2")])
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(define_insn "extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(sign_extend:SI (match_operand:QI 1 "general_operand" "rR,Q")))]
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"TARGET_40_PLUS"
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"*
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||
{
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rtx latehalf[2];
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||
|
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/* make register pair available */
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||
latehalf[0] = operands[0];
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operands[0] = gen_rtx_REG (HImode, REGNO (operands[0])+ 1);
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output_asm_insn(\"movb %1, %0\", operands);
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output_asm_insn(\"sxt %0\", latehalf);
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return \"\";
|
||
}"
|
||
[(set_attr "length" "2,3")])
|
||
|
||
;; maybe we have to use define_expand to say that we have the instruction,
|
||
;; unconditionally, and then match dependent on CPU type:
|
||
|
||
(define_expand "extendhisi2"
|
||
[(set (match_operand:SI 0 "general_operand" "=g")
|
||
(sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
|
||
""
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||
"")
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||
|
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(define_insn "" ; "extendhisi2"
|
||
[(set (match_operand:SI 0 "general_operand" "=o,<,r")
|
||
(sign_extend:SI (match_operand:HI 1 "general_operand" "g,g,g")))]
|
||
"TARGET_40_PLUS"
|
||
"*
|
||
{
|
||
rtx latehalf[2];
|
||
|
||
/* we don't want to mess with auto increment */
|
||
|
||
switch (which_alternative)
|
||
{
|
||
case 0:
|
||
|
||
latehalf[0] = operands[0];
|
||
operands[0] = adjust_address(operands[0], HImode, 2);
|
||
|
||
output_asm_insn(\"mov %1, %0\", operands);
|
||
output_asm_insn(\"sxt %0\", latehalf);
|
||
|
||
return \"\";
|
||
|
||
case 1:
|
||
|
||
/* - auto-decrement - right direction ;-) */
|
||
output_asm_insn(\"mov %1, %0\", operands);
|
||
output_asm_insn(\"sxt %0\", operands);
|
||
|
||
return \"\";
|
||
|
||
case 2:
|
||
|
||
/* make register pair available */
|
||
latehalf[0] = operands[0];
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
|
||
output_asm_insn(\"mov %1, %0\", operands);
|
||
output_asm_insn(\"sxt %0\", latehalf);
|
||
|
||
return \"\";
|
||
|
||
default:
|
||
|
||
gcc_unreachable ();
|
||
}
|
||
}"
|
||
[(set_attr "length" "5,3,3")])
|
||
|
||
|
||
(define_insn ""
|
||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||
(sign_extend:SI (match_operand:HI 1 "general_operand" "0")))]
|
||
"(! TARGET_40_PLUS)"
|
||
"*
|
||
{
|
||
static int count = 0;
|
||
char buf[100];
|
||
rtx lateoperands[2];
|
||
|
||
lateoperands[0] = operands[0];
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
|
||
output_asm_insn(\"tst %0\", operands);
|
||
sprintf(buf, \"bge extendhisi%d\", count);
|
||
output_asm_insn(buf, NULL);
|
||
output_asm_insn(\"mov -1, %0\", lateoperands);
|
||
sprintf(buf, \"bne extendhisi%d\", count+1);
|
||
output_asm_insn(buf, NULL);
|
||
sprintf(buf, \"\\nextendhisi%d:\", count);
|
||
output_asm_insn(buf, NULL);
|
||
output_asm_insn(\"clr %0\", lateoperands);
|
||
sprintf(buf, \"\\nextendhisi%d:\", count+1);
|
||
output_asm_insn(buf, NULL);
|
||
|
||
count += 2;
|
||
|
||
return \"\";
|
||
}"
|
||
[(set_attr "length" "6")])
|
||
|
||
;; make float to int and vice versa
|
||
;; using the cc_status.flag field we could probably cut down
|
||
;; on seti and setl
|
||
;; assume that we are normally in double and integer mode -
|
||
;; what do pdp library routines do to fpu mode ?
|
||
|
||
(define_insn "floatsidf2"
|
||
[(set (match_operand:DF 0 "register_operand" "=a,a,a")
|
||
(float:DF (match_operand:SI 1 "general_operand" "r,R,Q")))]
|
||
"TARGET_FPU"
|
||
"* if (which_alternative ==0)
|
||
{
|
||
rtx latehalf[2];
|
||
|
||
latehalf[0] = NULL;
|
||
latehalf[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
|
||
output_asm_insn(\"mov %1, -(sp)\", latehalf);
|
||
output_asm_insn(\"mov %1, -(sp)\", operands);
|
||
|
||
output_asm_insn(\"setl\", operands);
|
||
output_asm_insn(\"{ldcld|movif} (sp)+, %0\", operands);
|
||
output_asm_insn(\"seti\", operands);
|
||
return \"\";
|
||
}
|
||
else if (which_alternative == 1)
|
||
return \"setl\;{ldcld|movif} %1, %0\;seti\";
|
||
else
|
||
return \"setl\;{ldcld|movif} %1, %0\;seti\";
|
||
"
|
||
[(set_attr "length" "5,3,4")])
|
||
|
||
(define_insn "floathidf2"
|
||
[(set (match_operand:DF 0 "register_operand" "=a,a")
|
||
(float:DF (match_operand:HI 1 "general_operand" "rR,Qi")))]
|
||
"TARGET_FPU"
|
||
"{ldcid|movif} %1, %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;; cut float to int
|
||
(define_insn "fix_truncdfsi2"
|
||
[(set (match_operand:SI 0 "general_operand" "=r,R,Q")
|
||
(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a,a,a"))))]
|
||
"TARGET_FPU"
|
||
"* if (which_alternative ==0)
|
||
{
|
||
output_asm_insn(\"setl\", operands);
|
||
output_asm_insn(\"{stcdl|movfi} %1, -(sp)\", operands);
|
||
output_asm_insn(\"seti\", operands);
|
||
output_asm_insn(\"mov (sp)+, %0\", operands);
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
output_asm_insn(\"mov (sp)+, %0\", operands);
|
||
return \"\";
|
||
}
|
||
else if (which_alternative == 1)
|
||
return \"setl\;{stcdl|movfi} %1, %0\;seti\";
|
||
else
|
||
return \"setl\;{stcdl|movfi} %1, %0\;seti\";
|
||
"
|
||
[(set_attr "length" "5,3,4")])
|
||
|
||
(define_insn "fix_truncdfhi2"
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||
(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "a,a"))))]
|
||
"TARGET_FPU"
|
||
"{stcdi|movfi} %1, %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
|
||
;;- arithmetic instructions
|
||
;;- add instructions
|
||
|
||
(define_insn "adddf3"
|
||
[(set (match_operand:DF 0 "register_operand" "=a,a,a")
|
||
(plus:DF (match_operand:DF 1 "register_operand" "%0,0,0")
|
||
(match_operand:DF 2 "general_operand" "fR,Q,F")))]
|
||
"TARGET_FPU"
|
||
"{addd|addf} %2, %0"
|
||
[(set_attr "length" "1,2,5")])
|
||
|
||
(define_insn "addsi3"
|
||
[(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
|
||
(plus:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
|
||
(match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
|
||
""
|
||
"*
|
||
{ /* Here we trust that operands don't overlap
|
||
|
||
or is lateoperands the low word?? - looks like it! */
|
||
|
||
rtx lateoperands[3];
|
||
|
||
lateoperands[0] = operands[0];
|
||
|
||
if (REG_P (operands[0]))
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
else
|
||
operands[0] = adjust_address (operands[0], HImode, 2);
|
||
|
||
if (! CONSTANT_P(operands[2]))
|
||
{
|
||
lateoperands[2] = operands[2];
|
||
|
||
if (REG_P (operands[2]))
|
||
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
|
||
else
|
||
operands[2] = adjust_address (operands[2], HImode, 2);
|
||
|
||
output_asm_insn (\"add %2, %0\", operands);
|
||
output_asm_insn (\"adc %0\", lateoperands);
|
||
output_asm_insn (\"add %2, %0\", lateoperands);
|
||
return \"\";
|
||
}
|
||
|
||
lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff);
|
||
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
|
||
|
||
if (INTVAL(operands[2]))
|
||
{
|
||
output_asm_insn (\"add %2, %0\", operands);
|
||
output_asm_insn (\"adc %0\", lateoperands);
|
||
}
|
||
|
||
if (INTVAL(lateoperands[2]))
|
||
output_asm_insn (\"add %2, %0\", lateoperands);
|
||
|
||
return \"\";
|
||
}"
|
||
[(set_attr "length" "3,5,6,8,3,1,5,5,3,8")])
|
||
|
||
(define_insn "addhi3"
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
|
||
(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
|
||
(match_operand:HI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
|
||
""
|
||
"*
|
||
{
|
||
if (GET_CODE (operands[2]) == CONST_INT)
|
||
{
|
||
if (INTVAL(operands[2]) == 1)
|
||
return \"inc %0\";
|
||
else if (INTVAL(operands[2]) == -1)
|
||
return \"dec %0\";
|
||
}
|
||
|
||
return \"add %2, %0\";
|
||
}"
|
||
[(set_attr "length" "1,2,2,3")])
|
||
|
||
(define_insn "addqi3"
|
||
[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
|
||
(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
|
||
(match_operand:QI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
|
||
""
|
||
"*
|
||
{
|
||
if (GET_CODE (operands[2]) == CONST_INT)
|
||
{
|
||
if (INTVAL(operands[2]) == 1)
|
||
return \"incb %0\";
|
||
else if (INTVAL(operands[2]) == -1)
|
||
return \"decb %0\";
|
||
}
|
||
|
||
return \"add %2, %0\";
|
||
}"
|
||
[(set_attr "length" "1,2,2,3")])
|
||
|
||
|
||
;;- subtract instructions
|
||
;; we don't have to care for constant second
|
||
;; args, since they are canonical plus:xx now!
|
||
;; also for minus:DF ??
|
||
|
||
(define_insn "subdf3"
|
||
[(set (match_operand:DF 0 "register_operand" "=a,a")
|
||
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
|
||
(match_operand:DF 2 "general_operand" "fR,Q")))]
|
||
"TARGET_FPU"
|
||
"{subd|subf} %2, %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
(define_insn "subsi3"
|
||
[(set (match_operand:SI 0 "general_operand" "=r,r,o,o")
|
||
(minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
|
||
(match_operand:SI 2 "general_operand" "r,o,r,o")))]
|
||
""
|
||
"*
|
||
{ /* Here we trust that operands don't overlap
|
||
|
||
or is lateoperands the low word?? - looks like it! */
|
||
|
||
rtx lateoperands[3];
|
||
|
||
lateoperands[0] = operands[0];
|
||
|
||
if (REG_P (operands[0]))
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
else
|
||
operands[0] = adjust_address (operands[0], HImode, 2);
|
||
|
||
lateoperands[2] = operands[2];
|
||
|
||
if (REG_P (operands[2]))
|
||
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
|
||
else
|
||
operands[2] = adjust_address (operands[2], HImode, 2);
|
||
|
||
output_asm_insn (\"sub %2, %0\", operands);
|
||
output_asm_insn (\"sbc %0\", lateoperands);
|
||
output_asm_insn (\"sub %2, %0\", lateoperands);
|
||
return \"\";
|
||
}"
|
||
;; offsettable memory addresses always are expensive!!!
|
||
[(set_attr "length" "3,5,6,8")])
|
||
|
||
(define_insn "subhi3"
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
|
||
(minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
|
||
(match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))]
|
||
""
|
||
"*
|
||
{
|
||
gcc_assert (GET_CODE (operands[2]) != CONST_INT);
|
||
|
||
return \"sub %2, %0\";
|
||
}"
|
||
[(set_attr "length" "1,2,2,3")])
|
||
|
||
(define_insn "subqi3"
|
||
[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
|
||
(minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0")
|
||
(match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))]
|
||
""
|
||
"*
|
||
{
|
||
gcc_assert (GET_CODE (operands[2]) != CONST_INT);
|
||
|
||
return \"sub %2, %0\";
|
||
}"
|
||
[(set_attr "length" "1,2,2,3")])
|
||
|
||
;;;;- and instructions
|
||
;; Bit-and on the pdp (like on the VAX) is done with a clear-bits insn.
|
||
|
||
(define_insn "andsi3"
|
||
[(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
|
||
(and:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
|
||
(not:SI (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K"))))]
|
||
""
|
||
"*
|
||
{ /* Here we trust that operands don't overlap
|
||
|
||
or is lateoperands the low word?? - looks like it! */
|
||
|
||
rtx lateoperands[3];
|
||
|
||
lateoperands[0] = operands[0];
|
||
|
||
if (REG_P (operands[0]))
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
else
|
||
operands[0] = adjust_address (operands[0], HImode, 2);
|
||
|
||
if (! CONSTANT_P(operands[2]))
|
||
{
|
||
lateoperands[2] = operands[2];
|
||
|
||
if (REG_P (operands[2]))
|
||
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
|
||
else
|
||
operands[2] = adjust_address (operands[2], HImode, 2);
|
||
|
||
output_asm_insn (\"bic %2, %0\", operands);
|
||
output_asm_insn (\"bic %2, %0\", lateoperands);
|
||
return \"\";
|
||
}
|
||
|
||
lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff);
|
||
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
|
||
|
||
/* these have different lengths, so we should have
|
||
different constraints! */
|
||
if (INTVAL(operands[2]))
|
||
output_asm_insn (\"bic %2, %0\", operands);
|
||
|
||
if (INTVAL(lateoperands[2]))
|
||
output_asm_insn (\"bic %2, %0\", lateoperands);
|
||
|
||
return \"\";
|
||
}"
|
||
[(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
|
||
|
||
(define_insn "andhi3"
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
|
||
(and:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
|
||
(not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))]
|
||
""
|
||
"bic %2, %0"
|
||
[(set_attr "length" "1,2,2,3")])
|
||
|
||
(define_insn "andqi3"
|
||
[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
|
||
(and:QI (match_operand:QI 1 "general_operand" "0,0,0,0")
|
||
(not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))]
|
||
""
|
||
"bicb %2, %0"
|
||
[(set_attr "length" "1,2,2,3")])
|
||
|
||
;;- Bit set (inclusive or) instructions
|
||
(define_insn "iorsi3"
|
||
[(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
|
||
(ior:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
|
||
(match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
|
||
""
|
||
"*
|
||
{ /* Here we trust that operands don't overlap
|
||
|
||
or is lateoperands the low word?? - looks like it! */
|
||
|
||
rtx lateoperands[3];
|
||
|
||
lateoperands[0] = operands[0];
|
||
|
||
if (REG_P (operands[0]))
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
else
|
||
operands[0] = adjust_address (operands[0], HImode, 2);
|
||
|
||
if (! CONSTANT_P(operands[2]))
|
||
{
|
||
lateoperands[2] = operands[2];
|
||
|
||
if (REG_P (operands[2]))
|
||
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
|
||
else
|
||
operands[2] = adjust_address (operands[2], HImode, 2);
|
||
|
||
output_asm_insn (\"bis %2, %0\", operands);
|
||
output_asm_insn (\"bis %2, %0\", lateoperands);
|
||
return \"\";
|
||
}
|
||
|
||
lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff);
|
||
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
|
||
|
||
/* these have different lengths, so we should have
|
||
different constraints! */
|
||
if (INTVAL(operands[2]))
|
||
output_asm_insn (\"bis %2, %0\", operands);
|
||
|
||
if (INTVAL(lateoperands[2]))
|
||
output_asm_insn (\"bis %2, %0\", lateoperands);
|
||
|
||
return \"\";
|
||
}"
|
||
[(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
|
||
|
||
(define_insn "iorhi3"
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
|
||
(ior:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
|
||
(match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))]
|
||
""
|
||
"bis %2, %0"
|
||
[(set_attr "length" "1,2,2,3")])
|
||
|
||
(define_insn "iorqi3"
|
||
[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
|
||
(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
|
||
(match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))]
|
||
""
|
||
"bisb %2, %0")
|
||
|
||
;;- xor instructions
|
||
(define_insn "xorsi3"
|
||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||
(xor:SI (match_operand:SI 1 "register_operand" "%0")
|
||
(match_operand:SI 2 "arith_operand" "r")))]
|
||
"TARGET_40_PLUS"
|
||
"*
|
||
{ /* Here we trust that operands don't overlap */
|
||
|
||
rtx lateoperands[3];
|
||
|
||
lateoperands[0] = operands[0];
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
|
||
if (REG_P(operands[2]))
|
||
{
|
||
lateoperands[2] = operands[2];
|
||
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
|
||
|
||
output_asm_insn (\"xor %2, %0\", operands);
|
||
output_asm_insn (\"xor %2, %0\", lateoperands);
|
||
|
||
return \"\";
|
||
}
|
||
|
||
}"
|
||
[(set_attr "length" "2")])
|
||
|
||
(define_insn "xorhi3"
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||
(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
|
||
(match_operand:HI 2 "register_operand" "r,r")))]
|
||
"TARGET_40_PLUS"
|
||
"xor %2, %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;;- one complement instructions
|
||
|
||
(define_insn "one_cmplhi2"
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||
(not:HI (match_operand:HI 1 "general_operand" "0,0")))]
|
||
""
|
||
"com %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
(define_insn "one_cmplqi2"
|
||
[(set (match_operand:QI 0 "general_operand" "=rR,rR")
|
||
(not:QI (match_operand:QI 1 "general_operand" "0,g")))]
|
||
""
|
||
"@
|
||
comb %0
|
||
movb %1, %0\; comb %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;;- arithmetic shift instructions
|
||
(define_insn "ashlsi3"
|
||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||
(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
|
||
(match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||
"TARGET_45"
|
||
"ashc %2,%0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;; Arithmetic right shift on the pdp works by negating the shift count.
|
||
(define_expand "ashrsi3"
|
||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||
(ashift:SI (match_operand:SI 1 "register_operand" "0")
|
||
(match_operand:HI 2 "general_operand" "g")))]
|
||
""
|
||
"
|
||
{
|
||
operands[2] = negate_rtx (HImode, operands[2]);
|
||
}")
|
||
|
||
;; define asl aslb asr asrb - ashc missing!
|
||
|
||
;; asl
|
||
(define_insn ""
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||
(ashift:HI (match_operand:HI 1 "general_operand" "0,0")
|
||
(const_int 1)))]
|
||
""
|
||
"asl %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;; and another possibility for asr is << -1
|
||
;; might cause problems since -1 can also be encoded as 65535!
|
||
;; not in gcc2 ???
|
||
|
||
;; asr
|
||
(define_insn ""
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||
(ashift:HI (match_operand:HI 1 "general_operand" "0,0")
|
||
(const_int -1)))]
|
||
""
|
||
"asr %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;; lsr
|
||
(define_insn ""
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0")
|
||
(const_int 1)))]
|
||
""
|
||
"clc\;ror %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
(define_insn "lshrsi3"
|
||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
|
||
(const_int 1)))]
|
||
""
|
||
{
|
||
|
||
rtx lateoperands[2];
|
||
|
||
lateoperands[0] = operands[0];
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
|
||
lateoperands[1] = operands[1];
|
||
operands[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
|
||
|
||
output_asm_insn (\"clc\", operands);
|
||
output_asm_insn (\"ror %0\", lateoperands);
|
||
output_asm_insn (\"ror %0\", operands);
|
||
|
||
return \"\";
|
||
}
|
||
[(set_attr "length" "5")])
|
||
|
||
;; shift is by arbitrary count is expensive,
|
||
;; shift by one cheap - so let's do that, if
|
||
;; space doesn't matter
|
||
(define_insn ""
|
||
[(set (match_operand:HI 0 "general_operand" "=r")
|
||
(ashift:HI (match_operand:HI 1 "general_operand" "0")
|
||
(match_operand:HI 2 "expand_shift_operand" "O")))]
|
||
"! optimize_size"
|
||
"*
|
||
{
|
||
register int i;
|
||
|
||
for (i = 1; i <= abs(INTVAL(operands[2])); i++)
|
||
if (INTVAL(operands[2]) < 0)
|
||
output_asm_insn(\"asr %0\", operands);
|
||
else
|
||
output_asm_insn(\"asl %0\", operands);
|
||
|
||
return \"\";
|
||
}"
|
||
;; longest is 4
|
||
[(set (attr "length") (const_int 4))])
|
||
|
||
;; aslb
|
||
(define_insn ""
|
||
[(set (match_operand:QI 0 "general_operand" "=r,o")
|
||
(ashift:QI (match_operand:QI 1 "general_operand" "0,0")
|
||
(match_operand:HI 2 "const_immediate_operand" "n,n")))]
|
||
""
|
||
"*
|
||
{ /* allowing predec or post_inc is possible, but hairy! */
|
||
int i, cnt;
|
||
|
||
cnt = INTVAL(operands[2]) & 0x0007;
|
||
|
||
for (i=0 ; i < cnt ; i++)
|
||
output_asm_insn(\"aslb %0\", operands);
|
||
|
||
return \"\";
|
||
}"
|
||
;; set attribute length ( match_dup 2 & 7 ) *(1 or 2) !!!
|
||
[(set_attr_alternative "length"
|
||
[(const_int 7)
|
||
(const_int 14)])])
|
||
|
||
;;; asr
|
||
;(define_insn ""
|
||
; [(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||
; (ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0")
|
||
; (const_int 1)))]
|
||
; ""
|
||
; "asr %0"
|
||
; [(set_attr "length" "1,2")])
|
||
|
||
;; asrb
|
||
(define_insn ""
|
||
[(set (match_operand:QI 0 "general_operand" "=r,o")
|
||
(ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0")
|
||
(match_operand:HI 2 "const_immediate_operand" "n,n")))]
|
||
""
|
||
"*
|
||
{ /* allowing predec or post_inc is possible, but hairy! */
|
||
int i, cnt;
|
||
|
||
cnt = INTVAL(operands[2]) & 0x0007;
|
||
|
||
for (i=0 ; i < cnt ; i++)
|
||
output_asm_insn(\"asrb %0\", operands);
|
||
|
||
return \"\";
|
||
}"
|
||
[(set_attr_alternative "length"
|
||
[(const_int 7)
|
||
(const_int 14)])])
|
||
|
||
;; the following is invalid - too complex!!! - just say 14 !!!
|
||
; [(set (attr "length") (plus (and (match_dup 2)
|
||
; (const_int 7))
|
||
; (and (match_dup 2)
|
||
; (const_int 7))))])
|
||
|
||
|
||
|
||
;; can we get +-1 in the next pattern? should
|
||
;; have been caught by previous patterns!
|
||
|
||
(define_insn "ashlhi3"
|
||
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
||
(ashift:HI (match_operand:HI 1 "register_operand" "0,0")
|
||
(match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||
""
|
||
"*
|
||
{
|
||
if (GET_CODE(operands[2]) == CONST_INT)
|
||
{
|
||
if (INTVAL(operands[2]) == 1)
|
||
return \"asl %0\";
|
||
else if (INTVAL(operands[2]) == -1)
|
||
return \"asr %0\";
|
||
}
|
||
|
||
return \"ash %2,%0\";
|
||
}"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;; Arithmetic right shift on the pdp works by negating the shift count.
|
||
(define_expand "ashrhi3"
|
||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||
(ashift:HI (match_operand:HI 1 "register_operand" "0")
|
||
(match_operand:HI 2 "general_operand" "g")))]
|
||
""
|
||
"
|
||
{
|
||
operands[2] = negate_rtx (HImode, operands[2]);
|
||
}")
|
||
|
||
;;;;- logical shift instructions
|
||
;;(define_insn "lshrsi3"
|
||
;; [(set (match_operand:HI 0 "register_operand" "=r")
|
||
;; (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
|
||
;; (match_operand:HI 2 "arith_operand" "rI")))]
|
||
;; ""
|
||
;; "srl %0,%2")
|
||
|
||
;; absolute
|
||
|
||
(define_insn "absdf2"
|
||
[(set (match_operand:DF 0 "general_operand" "=fR,Q")
|
||
(abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
|
||
"TARGET_FPU"
|
||
"{absd|absf} %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
(define_insn "abshi2"
|
||
[(set (match_operand:HI 0 "general_operand" "=r,o")
|
||
(abs:HI (match_operand:HI 1 "general_operand" "0,0")))]
|
||
"TARGET_ABSHI_BUILTIN"
|
||
"*
|
||
{
|
||
static int count = 0;
|
||
char buf[200];
|
||
|
||
output_asm_insn(\"tst %0\", operands);
|
||
sprintf(buf, \"bge abshi%d\", count);
|
||
output_asm_insn(buf, NULL);
|
||
output_asm_insn(\"neg %0\", operands);
|
||
sprintf(buf, \"\\nabshi%d:\", count++);
|
||
output_asm_insn(buf, NULL);
|
||
|
||
return \"\";
|
||
}"
|
||
[(set_attr "length" "3,5")])
|
||
|
||
|
||
;; define expand abshi - is much better !!! - but
|
||
;; will it be optimized into an abshi2 ?
|
||
;; it will leave better code, because the tsthi might be
|
||
;; optimized away!!
|
||
; -- just a thought - don't have time to check
|
||
;
|
||
;(define_expand "abshi2"
|
||
; [(match_operand:HI 0 "general_operand" "")
|
||
; (match_operand:HI 1 "general_operand" "")]
|
||
; ""
|
||
; "
|
||
;{
|
||
; rtx label = gen_label_rtx ();
|
||
;
|
||
; /* do I need this? */
|
||
; do_pending_stack_adjust ();
|
||
;
|
||
; emit_move_insn (operands[0], operands[1]);
|
||
;
|
||
; emit_insn (gen_tsthi (operands[0]));
|
||
; emit_insn (gen_bge (label1));
|
||
;
|
||
; emit_insn (gen_neghi(operands[0], operands[0])
|
||
;
|
||
; emit_barrier ();
|
||
;
|
||
; emit_label (label);
|
||
;
|
||
; /* allow REG_NOTES to be set on last insn (labels don't have enough
|
||
; fields, and can't be used for REG_NOTES anyway). */
|
||
; emit_use (stack_pointer_rtx);
|
||
; DONE;
|
||
;}")
|
||
|
||
;; negate insns
|
||
|
||
(define_insn "negdf2"
|
||
[(set (match_operand:DF 0 "general_operand" "=fR,Q")
|
||
(neg:DF (match_operand:DF 1 "register_operand" "0,0")))]
|
||
"TARGET_FPU"
|
||
"{negd|negf} %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
(define_insn "negsi2"
|
||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||
(neg:SI (match_operand:SI 1 "general_operand" "0")))]
|
||
""
|
||
{
|
||
|
||
rtx lateoperands[2];
|
||
|
||
lateoperands[0] = operands[0];
|
||
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
|
||
|
||
lateoperands[1] = operands[1];
|
||
operands[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
|
||
|
||
output_asm_insn (\"com %0\", operands);
|
||
output_asm_insn (\"com %0\", lateoperands);
|
||
output_asm_insn (\"inc %0\", operands);
|
||
output_asm_insn (\"adc %0\", lateoperands);
|
||
|
||
return \"\";
|
||
}
|
||
[(set_attr "length" "5")])
|
||
|
||
(define_insn "neghi2"
|
||
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||
(neg:HI (match_operand:HI 1 "general_operand" "0,0")))]
|
||
""
|
||
"neg %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
(define_insn "negqi2"
|
||
[(set (match_operand:QI 0 "general_operand" "=rR,Q")
|
||
(neg:QI (match_operand:QI 1 "general_operand" "0,0")))]
|
||
""
|
||
"negb %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
|
||
;; Unconditional and other jump instructions
|
||
(define_insn "jump"
|
||
[(set (pc)
|
||
(label_ref (match_operand 0 "" "")))]
|
||
""
|
||
"jmp %l0"
|
||
[(set_attr "length" "2")])
|
||
|
||
(define_insn ""
|
||
[(set (pc)
|
||
(label_ref (match_operand 0 "" "")))
|
||
(clobber (const_int 1))]
|
||
""
|
||
"jmp %l0"
|
||
[(set_attr "length" "2")])
|
||
|
||
(define_insn "tablejump"
|
||
[(set (pc) (match_operand:HI 0 "general_operand" "rR,Q"))
|
||
(use (label_ref (match_operand 1 "" "")))]
|
||
""
|
||
"jmp %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;; indirect jump - let's be conservative!
|
||
;; allow only register_operand, even though we could also
|
||
;; allow labels etc.
|
||
|
||
(define_insn "indirect_jump"
|
||
[(set (pc) (match_operand:HI 0 "register_operand" "r"))]
|
||
""
|
||
"jmp (%0)")
|
||
|
||
;;- jump to subroutine
|
||
|
||
(define_insn "call"
|
||
[(call (match_operand:HI 0 "general_operand" "rR,Q")
|
||
(match_operand:HI 1 "general_operand" "g,g"))
|
||
;; (use (reg:HI 0)) what was that ???
|
||
]
|
||
;;- Don't use operand 1 for most machines.
|
||
""
|
||
"jsr pc, %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;;- jump to subroutine
|
||
(define_insn "call_value"
|
||
[(set (match_operand 0 "" "")
|
||
(call (match_operand:HI 1 "general_operand" "rR,Q")
|
||
(match_operand:HI 2 "general_operand" "g,g")))
|
||
;; (use (reg:HI 0)) - what was that ????
|
||
]
|
||
;;- Don't use operand 2 for most machines.
|
||
""
|
||
"jsr pc, %1"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;;- nop instruction
|
||
(define_insn "nop"
|
||
[(const_int 0)]
|
||
""
|
||
"nop")
|
||
|
||
|
||
;;- multiply
|
||
|
||
(define_insn "muldf3"
|
||
[(set (match_operand:DF 0 "register_operand" "=a,a,a")
|
||
(mult:DF (match_operand:DF 1 "register_operand" "%0,0,0")
|
||
(match_operand:DF 2 "general_operand" "fR,Q,F")))]
|
||
"TARGET_FPU"
|
||
"{muld|mulf} %2, %0"
|
||
[(set_attr "length" "1,2,5")])
|
||
|
||
;; 16 bit result multiply:
|
||
;; currently we multiply only into odd registers, so we don't use two
|
||
;; registers - but this is a bit inefficient at times. If we define
|
||
;; a register class for each register, then we can specify properly
|
||
;; which register need which scratch register ....
|
||
|
||
(define_insn "mulhi3"
|
||
[(set (match_operand:HI 0 "register_operand" "=d,d") ; multiply regs
|
||
(mult:HI (match_operand:HI 1 "register_operand" "%0,0")
|
||
(match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||
"TARGET_45"
|
||
"mul %2, %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;; 32 bit result
|
||
(define_expand "mulhisi3"
|
||
[(set (match_dup 3)
|
||
(match_operand:HI 1 "general_operand" "g,g"))
|
||
(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
|
||
(mult:SI (truncate:HI
|
||
(match_dup 0))
|
||
(match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||
"TARGET_45"
|
||
"operands[3] = gen_lowpart(HImode, operands[1]);")
|
||
|
||
(define_insn ""
|
||
[(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
|
||
(mult:SI (truncate:HI
|
||
(match_operand:SI 1 "register_operand" "%0,0"))
|
||
(match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||
"TARGET_45"
|
||
"mul %2, %0"
|
||
[(set_attr "length" "1,2")])
|
||
|
||
;(define_insn "mulhisi3"
|
||
; [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
|
||
; (mult:SI (truncate:HI
|
||
; (match_operand:SI 1 "register_operand" "%0,0"))
|
||
; (match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||
; "TARGET_45"
|
||
; "mul %2, %0"
|
||
; [(set_attr "length" "1,2")])
|
||
|
||
;;- divide
|
||
(define_insn "divdf3"
|
||
[(set (match_operand:DF 0 "register_operand" "=a,a,a")
|
||
(div:DF (match_operand:DF 1 "register_operand" "0,0,0")
|
||
(match_operand:DF 2 "general_operand" "fR,Q,F")))]
|
||
"TARGET_FPU"
|
||
"{divd|divf} %2, %0"
|
||
[(set_attr "length" "1,2,5")])
|
||
|
||
|
||
(define_expand "divhi3"
|
||
[(set (subreg:HI (match_dup 1) 0)
|
||
(div:HI (match_operand:SI 1 "general_operand" "0")
|
||
(match_operand:HI 2 "general_operand" "g")))
|
||
(set (match_operand:HI 0 "general_operand" "=r")
|
||
(subreg:HI (match_dup 1) 0))]
|
||
"TARGET_45"
|
||
"")
|
||
|
||
(define_insn ""
|
||
[(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0)
|
||
(div:HI (match_operand:SI 1 "general_operand" "0")
|
||
(match_operand:HI 2 "general_operand" "g")))]
|
||
"TARGET_45"
|
||
"div %2,%0"
|
||
[(set_attr "length" "2")])
|
||
|
||
(define_expand "modhi3"
|
||
[(set (subreg:HI (match_dup 1) 2)
|
||
(mod:HI (match_operand:SI 1 "general_operand" "0")
|
||
(match_operand:HI 2 "general_operand" "g")))
|
||
(set (match_operand:HI 0 "general_operand" "=r")
|
||
(subreg:HI (match_dup 1) 2))]
|
||
"TARGET_45"
|
||
"")
|
||
|
||
(define_insn ""
|
||
[(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 2)
|
||
(mod:HI (match_operand:SI 1 "general_operand" "0")
|
||
(match_operand:HI 2 "general_operand" "g")))]
|
||
"TARGET_45"
|
||
"div %2,%0"
|
||
[(set_attr "length" "2")])
|
||
|
||
;(define_expand "divmodhi4"
|
||
; [(parallel [(set (subreg:HI (match_dup 1) 0)
|
||
; (div:HI (match_operand:SI 1 "general_operand" "0")
|
||
; (match_operand:HI 2 "general_operand" "g")))
|
||
; (set (subreg:HI (match_dup 1) 2)
|
||
; (mod:HI (match_dup 1)
|
||
; (match_dup 2)))])
|
||
; (set (match_operand:HI 3 "general_operand" "=r")
|
||
; (subreg:HI (match_dup 1) 2))
|
||
; (set (match_operand:HI 0 "general_operand" "=r")
|
||
; (subreg:HI (match_dup 1) 0))]
|
||
; "TARGET_45"
|
||
; "")
|
||
;
|
||
;(define_insn ""
|
||
; [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0)
|
||
; (div:HI (match_operand:SI 1 "general_operand" "0")
|
||
; (match_operand:HI 2 "general_operand" "g")))
|
||
; (set (subreg:HI (match_dup 0) 2)
|
||
; (mod:HI (match_dup 1)
|
||
; (match_dup 2)))]
|
||
; "TARGET_45"
|
||
; "div %2, %0")
|
||
;
|
||
|
||
;; is rotate doing the right thing to be included here ????
|