467 lines
13 KiB
Markdown
467 lines
13 KiB
Markdown
;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005, 2007, 2008
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; move, push, extend, etc.
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;; Be careful to never create an alternative that has memory as both
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;; src and dest, as that makes gcc think that mem-mem moves in general
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;; are supported. While the chip does support this, it only has two
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;; address registers and sometimes gcc requires more than that. One
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;; example is code like this: a = *b where both a and b are spilled to
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;; the stack.
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;; Match push/pop before mov.b for passing char as arg,
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;; e.g. stdlib/efgcvt.c.
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(define_insn "movqi_op"
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[(set (match_operand:QI 0 "m32c_nonimmediate_operand"
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"=Rqi*Rmm, <, RqiSd*Rmm, SdSs, Rqi*Rmm, Sd")
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(match_operand:QI 1 "m32c_any_operand"
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"iRqi*Rmm, iRqiSd*Rmm, >, Rqi*Rmm, SdSs, i"))]
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"m32c_mov_ok (operands, QImode)"
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"@
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mov.b\t%1,%0
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push.b\t%1
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pop.b\t%0
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mov.b\t%1,%0
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mov.b\t%1,%0
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mov.b\t%1,%0"
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[(set_attr "flags" "sz,*,*,sz,sz,sz")]
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)
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(define_expand "movqi"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=RqiSd*Rmm")
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(match_operand:QI 1 "general_operand" "iRqiSd*Rmm"))]
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""
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"if (m32c_prepare_move (operands, QImode)) DONE;"
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)
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(define_insn "movhi_op"
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[(set (match_operand:HI 0 "m32c_nonimmediate_operand"
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"=Rhi*Rmm, Sd, SdSs, *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
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(match_operand:HI 1 "m32c_any_operand"
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"iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
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"m32c_mov_ok (operands, HImode)"
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"@
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mov.w\t%1,%0
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mov.w\t%1,%0
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mov.w\t%1,%0
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ldc\t%1,%0
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stc\t%1,%0
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push.w\t%1
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pop.w\t%0
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pushc\t%1
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popc\t%0"
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[(set_attr "flags" "sz,sz,sz,n,n,n,n,n,n")]
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)
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(define_expand "movhi"
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[(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
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(match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
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""
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"if (m32c_prepare_move (operands, HImode)) DONE;"
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)
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(define_insn "movpsi_op"
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[(set (match_operand:PSI 0 "m32c_nonimmediate_operand"
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"=Raa, SdRmmRpi, Rcl, RpiSd*Rmm, <, <, Rcl, RpiRaa*Rmm")
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(match_operand:PSI 1 "m32c_any_operand"
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"sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))]
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"TARGET_A24 && m32c_mov_ok (operands, PSImode)"
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"@
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mov.l:s\t%1,%0
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mov.l\t%1,%0
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ldc\t%1,%0
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stc\t%1,%0
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push.l\t%1
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pushc\t%1
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popc\t%0
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#"
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[(set_attr "flags" "sz,sz,n,n,n,n,n,*")]
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)
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;; The intention here is to combine the add with the move to create an
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;; indexed move. GCC doesn't always figure this out itself.
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(define_peephole2
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[(set (match_operand:HPSI 0 "register_operand" "")
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(plus:HPSI (match_operand:HPSI 1 "register_operand" "")
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(match_operand:HPSI 2 "immediate_operand" "")))
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(set (match_operand:QHSI 3 "nonimmediate_operand" "")
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(mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
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"REGNO (operands[0]) == REGNO (operands[1])
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&& REGNO (operands[0]) == REGNO (operands[4])
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&& (rtx_equal_p (operands[0], operands[3])
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|| (dead_or_set_p (peep2_next_insn (1), operands[4])
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&& ! reg_mentioned_p (operands[0], operands[3])))"
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[(set (match_dup 3)
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(mem:QHSI (plus:HPSI (match_dup 1)
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(match_dup 2))))]
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"")
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(define_peephole2
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[(set (match_operand:HPSI 0 "register_operand" "")
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(plus:HPSI (match_operand:HPSI 1 "register_operand" "")
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(match_operand:HPSI 2 "immediate_operand" "")))
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(set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
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(match_operand:QHSI 3 "m32c_any_operand" ""))]
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"REGNO (operands[0]) == REGNO (operands[1])
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&& REGNO (operands[0]) == REGNO (operands[4])
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&& dead_or_set_p (peep2_next_insn (1), operands[4])
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&& ! reg_mentioned_p (operands[0], operands[3])"
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[(set (mem:QHSI (plus:HPSI (match_dup 1)
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(match_dup 2)))
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(match_dup 3))]
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"")
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; Peephole to generate SImode mov instructions for storing an
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; immediate double data to a memory location.
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(define_peephole2
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[(set (match_operand:HI 0 "memory_operand" "")
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(match_operand 1 "const_int_operand" ""))
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(set (match_operand:HI 2 "memory_operand" "")
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(match_operand 3 "const_int_operand" ""))]
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"TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
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[(set (match_dup 4) (match_dup 5))]
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""
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)
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; Some PSI moves must be split.
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(define_split
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[(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
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(match_operand:PSI 1 "m32c_any_operand" ""))]
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"reload_completed && m32c_split_psi_p (operands)"
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[(set (match_dup 2)
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(match_dup 3))
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(set (match_dup 4)
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(match_dup 5))]
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"m32c_split_move (operands, PSImode, 3);"
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)
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(define_expand "movpsi"
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[(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
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(match_operand:PSI 1 "m32c_any_operand" ""))]
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""
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"if (m32c_prepare_move (operands, PSImode)) DONE;"
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)
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(define_expand "movsi"
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[(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm")
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(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm"))]
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""
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"if (m32c_split_move (operands, SImode, 0)) DONE;"
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)
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; All SI moves are split if TARGET_A16
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(define_insn_and_split "movsi_splittable"
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[(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi<*Rmm,RsiSd*Rmm,Ss")
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(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm,iRsi>*Rmm,Rsi*Rmm"))]
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"TARGET_A16"
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"#"
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"TARGET_A16 && reload_completed"
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[(pc)]
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"m32c_split_move (operands, SImode, 1); DONE;"
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)
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; The movsi pattern doesn't always match because sometimes the modes
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; don't match.
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(define_insn "push_a01_l"
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[(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
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(match_operand 0 "a_operand" "Raa"))]
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""
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"push.l\t%0"
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[(set_attr "flags" "n")]
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)
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(define_insn "movsi_24"
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[(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi*Rmm, Sd, RsiSd*Rmm, <")
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(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
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"TARGET_A24"
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"@
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mov.l\t%1,%0
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mov.l\t%1,%0
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#
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push.l\t%1"
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[(set_attr "flags" "sz,sz,*,n")]
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)
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(define_expand "movdi"
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[(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=RdiSd*Rmm")
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(match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm"))]
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""
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"if (m32c_split_move (operands, DImode, 0)) DONE;"
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)
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(define_insn_and_split "movdi_splittable"
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[(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=Rdi<*Rmm,RdiSd*Rmm")
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(match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
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""
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"#"
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"reload_completed"
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[(pc)]
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"m32c_split_move (operands, DImode, 1); DONE;"
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)
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(define_insn "pushqi"
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[(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
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(match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
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""
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"push.b\t%0"
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[(set_attr "flags" "n")]
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)
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(define_expand "pushhi"
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[(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
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(match_operand:HI 0 "" ""))]
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""
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"if (TARGET_A16)
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gen_pushhi_16 (operands[0]);
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else
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gen_pushhi_24 (operands[0]);
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DONE;"
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)
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(define_insn "pushhi_16"
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[(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
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(match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
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"TARGET_A16"
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"@
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push.w\t%0
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pushc\t%0"
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[(set_attr "flags" "n,n")]
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)
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(define_insn "pushhi_24"
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[(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
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(match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
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"TARGET_A24"
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"push.w\t%0"
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[(set_attr "flags" "n")]
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)
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;(define_insn "pushpi"
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; [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
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; (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
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; "TARGET_A24"
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; "@
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; push.l\t%0
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; pushc\t%0"
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; )
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(define_insn "pushsi"
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[(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
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(match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
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"TARGET_A24"
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"push.l\t%0"
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[(set_attr "flags" "n")]
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)
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(define_expand "pophi"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
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(mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
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""
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"if (TARGET_A16)
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gen_pophi_16 (operands[0]);
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else
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gen_pophi_24 (operands[0]);
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DONE;"
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)
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(define_insn "pophi_16"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
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(mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
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"TARGET_A16"
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"@
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pop.w\t%0
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popc\t%0"
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[(set_attr "flags" "n,n")]
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)
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(define_insn "pophi_24"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
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(mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
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"TARGET_A24"
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"pop.w\t%0"
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[(set_attr "flags" "n")]
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)
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(define_insn "poppsi"
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[(set (match_operand:PSI 0 "cr_operand" "=Rcl")
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(mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
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"TARGET_A24"
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"popc\t%0"
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[(set_attr "flags" "n")]
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)
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;; Rhl used here as an HI-mode Rxl
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(define_insn "extendqihi2"
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[(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhlSd*Rmm")
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(sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
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""
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"exts.b\t%1"
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[(set_attr "flags" "sz")]
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)
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(define_insn "extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "=R03")
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(sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
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""
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"*
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if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
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else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
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[(set_attr "flags" "x")]
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)
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(define_insn "extendhipsi2"
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[(set (match_operand:PSI 0 "register_operand" "=R03")
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(sign_extend:PSI (match_operand:HI 1 "register_operand" "0")))]
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""
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"*
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if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
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else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
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[(set_attr "flags" "x")]
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)
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(define_insn "extendpsisi2"
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[(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
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(sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
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""
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"; expand psi %1 to si %0"
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[(set_attr "flags" "n")]
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)
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(define_insn "zero_extendpsisi2"
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[(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
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(zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
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""
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"; expand psi %1 to si %0"
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[(set_attr "flags" "n")]
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)
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(define_insn "zero_extendhipsi2"
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[(set (match_operand:PSI 0 "register_operand" "=Raa")
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(truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
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""
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"mov.w\t%1,%0"
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[(set_attr "flags" "sz")]
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)
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(define_insn "zero_extendhisi2"
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[(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd")
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(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
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""
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"mov.w\t#0,%H0"
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[(set_attr "flags" "x")]
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)
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(define_insn "zero_extendqihi2"
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[(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=?Rhl,RhiSd*Rmm")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
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""
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"@
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mov.b\t#0,%H0
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and.w\t#255,%0"
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[(set_attr "flags" "x,x")]
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)
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(define_insn "truncsipsi2_16"
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[(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
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(truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
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"TARGET_A16"
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"@
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; no-op trunc si %1 to psi %0
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#
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ldc\t%1,%0
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stc\t%1,%0"
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[(set_attr "flags" "n,*,n,n")]
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)
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(define_insn "trunchiqi2"
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[(set (match_operand:QI 0 "m32c_nonimmediate_operand" "=RqiRmmSd")
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(truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
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""
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"; no-op trunc hi %1 to qi %0"
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[(set_attr "flags" "n")]
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)
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(define_insn "truncsipsi2_24"
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[(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
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(truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
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"TARGET_A24"
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"@
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; no-op trunc si %1 to psi %0
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mov.l\t%1,%0
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ldc\t%1,%0
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stc\t%1,%0"
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[(set_attr "flags" "n,sz,n,n")]
|
|
)
|
|
|
|
(define_expand "truncsipsi2"
|
|
[(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
|
|
(truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
|
|
""
|
|
""
|
|
)
|
|
|
|
(define_expand "reload_inqi"
|
|
[(set (match_operand:QI 2 "" "=&Rqi")
|
|
(match_operand:QI 1 "" ""))
|
|
(set (match_operand:QI 0 "" "")
|
|
(match_dup 2))
|
|
]
|
|
""
|
|
"")
|
|
|
|
(define_expand "reload_outqi"
|
|
[(set (match_operand:QI 2 "" "=&Rqi")
|
|
(match_operand:QI 1 "" ""))
|
|
(set (match_operand:QI 0 "" "")
|
|
(match_dup 2))
|
|
]
|
|
""
|
|
"")
|
|
|
|
(define_expand "reload_inhi"
|
|
[(set (match_operand:HI 2 "" "=&Rhi")
|
|
(match_operand:HI 1 "" ""))
|
|
(set (match_operand:HI 0 "" "")
|
|
(match_dup 2))
|
|
]
|
|
""
|
|
"")
|
|
|
|
(define_expand "reload_outhi"
|
|
[(set (match_operand:HI 2 "" "=&Rhi")
|
|
(match_operand:HI 1 "" ""))
|
|
(set (match_operand:HI 0 "" "")
|
|
(match_dup 2))
|
|
]
|
|
""
|
|
"")
|