249 lines
7.4 KiB
Markdown
249 lines
7.4 KiB
Markdown
;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005, 2007
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; add, sub
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(define_insn "addqi3"
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[(set (match_operand:QI 0 "mra_or_sp_operand"
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"=SdRhl,SdRhl,??Rmm,??Rmm, *Raa,*Raa,SdRhl,??Rmm")
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(plus:QI (match_operand:QI 1 "mra_operand"
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"%0,0,0,0, 0,0,0,0")
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(match_operand:QI 2 "mrai_operand"
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"iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,*Raa,*Raa")))]
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""
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"add.b\t%2,%0"
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[(set_attr "flags" "oszc")]
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)
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(define_insn "addhi3"
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[(set (match_operand:HI 0 "m32c_nonimmediate_operand"
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"=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, Raw, Raw, !Rsp")
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(plus:HI (match_operand:HI 1 "m32c_any_operand"
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"%0,0,0,0, 0,0, Raw, Rfb, Rfb, 0")
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(match_operand:HI 2 "m32c_any_operand"
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"IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, I00, IS1, i")))]
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""
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"@
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add.w\t%2,%0
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add.w\t%2,%0
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add.w\t%2,%0
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add.w\t%2,%0
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sub.w\t%m2,%0
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sub.w\t%m2,%0
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mova\t%d2[%1],%0
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stc\t%1,%0
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mova\t%D2[%1],%0
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add.w\t%2,%0"
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[(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc")]
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)
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(define_insn "addpsi3"
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[(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=Rpi,Raa,SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi")
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(plus:PSI (match_operand:PSI 1 "m32c_nonimmediate_operand" "0,0,0,0,0, Raa,Rad")
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(match_operand:PSI 2 "m32c_any_operand" "Is3,IS1,iSdRpi,?Rmm,i, i,IS2")))]
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"TARGET_A24"
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"@
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add.l:q\t%2,%0
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addx\t%2,%0
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add.l\t%2,%0
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add.l\t%2,%0
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add.l\t%2,%0
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mova\t%d2[%1],%0
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mova\t%D2[%1],%0"
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[(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")]
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)
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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"TARGET_A24 ||TARGET_A16"
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""
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)
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(define_insn "addsi3_1"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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(plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
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(match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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"TARGET_A16"
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"*
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switch (which_alternative)
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{
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case 0:
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return \"add.w %X2,%h0\;adcf.w %H0\";
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case 1:
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return \"add.w %X2,%h0\;adcf.w %H0\";
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case 2:
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output_asm_insn (\"add.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"adc.w %X2,%H0\";
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case 3:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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case 4:
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output_asm_insn (\"add.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"adc.w %X2,%H0\";
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case 5:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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case 6:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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case 7:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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}"
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[(set_attr "flags" "x,x,x,x,x,x,x,x")]
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)
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(define_insn "addsi3_2"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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"TARGET_A24"
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"add.l\t%2,%0"
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[(set_attr "flags" "oszc")]
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)
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(define_insn "subqi3"
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[(set (match_operand:QI 0 "mra_or_sp_operand"
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"=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
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(minus:QI (match_operand:QI 1 "mra_operand"
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"0,0,0,0, 0,0,0,0, 0")
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(match_operand:QI 2 "mrai_operand"
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"iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i")))]
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""
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"sub.b\t%2,%0"
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[(set_attr "flags" "oszc")]
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)
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(define_insn "subhi3"
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[(set (match_operand:HI 0 "mra_operand"
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"=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm")
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(minus:HI (match_operand:HI 1 "mras_operand"
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"0,0,0,0, 0,0")
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(match_operand:HI 2 "mrai_operand"
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"IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2")))]
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""
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"@
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sub.w\t%2,%0
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sub.w\t%2,%0
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sub.w\t%2,%0
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sub.w\t%2,%0
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add.w\t%m2,%0
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add.w\t%m2,%0"
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[(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")]
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)
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(define_insn "subpsi3"
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[(set (match_operand:PSI 0 "mra_operand" "=RpiSd,RpiSd,??Rmm,??Rmm")
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(minus:PSI (match_operand:PSI 1 "mra_operand" "0,0,0,0")
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(match_operand:PSI 2 "mrai_operand" "iRpiSd,?Rmm,iRpiSd,?Rmm")))]
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"TARGET_A24"
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"sub.%&\t%2,%0"
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[(set_attr "flags" "oszc")]
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)
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(define_expand "subsi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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"TARGET_A24 ||TARGET_A16"
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""
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)
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(define_insn "subsi3_1"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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(minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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"TARGET_A16"
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"*
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switch (which_alternative)
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{
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case 0:
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output_asm_insn (\"sub.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"sbb.w %X2,%H0\";
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case 1:
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return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
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case 2:
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output_asm_insn (\"sub.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"sbb.w %X2,%H0\";
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case 3:
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return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
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case 4:
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return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
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case 5:
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return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
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}"
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[(set_attr "flags" "x,x,x,x,x,x")]
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)
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(define_insn "subsi3_2"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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"TARGET_A24"
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"sub.l\t%2,%0"
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[(set_attr "flags" "oszc,oszc,oszc,oszc")]
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)
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(define_insn "negqi2"
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[(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
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(neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]
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""
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"neg.b\t%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "neghi2"
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[(set (match_operand:HI 0 "mra_operand" "=SdRhi,??Rmm")
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(neg:HI (match_operand:HI 1 "mra_operand" "0,0")))]
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""
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"neg.w\t%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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; We can negate an SImode by operating on the subparts. GCC deals
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; with this itself for larger modes, but not SI.
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(define_insn "negsi2"
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[(set (match_operand:SI 0 "mra_operand" "=SdR03,??Rmm")
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(neg:SI (match_operand:SI 1 "mra_operand" "0,0")))]
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""
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"not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0"
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[(set_attr "flags" "x")]
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)
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(define_insn "absqi2"
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[(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
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(abs:QI (match_operand:QI 1 "mra_operand" "0,0")))]
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""
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"abs.b\t%0"
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[(set_attr "flags" "oszc")]
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)
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(define_insn "abshi2"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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(abs:HI (match_operand:HI 1 "mra_operand" "0,0")))]
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""
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"abs.w\t%0"
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[(set_attr "flags" "oszc")]
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)
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