148 lines
4.7 KiB
Markdown
148 lines
4.7 KiB
Markdown
;; Constraint definitions for IA-64
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;; Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Register constraints
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(define_register_constraint "a" "ADDL_REGS"
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"addl register")
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(define_register_constraint "b" "BR_REGS"
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"branch register")
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(define_register_constraint "c" "PR_REGS"
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"predicate register")
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(define_register_constraint "d" "AR_M_REGS"
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"memory pipeline application register")
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(define_register_constraint "e" "AR_I_REGS"
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"integer pipeline application register")
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(define_register_constraint "f" "FR_REGS"
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"floating-point register")
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(define_register_constraint "x" "FP_REGS"
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"floating-point register, excluding f31 and f127, used for fldp")
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;; Integer constraints
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(define_constraint "I"
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"14 bit signed immediate for arithmetic instructions"
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT)ival + 0x2000 < 0x4000")))
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(define_constraint "J"
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"22 bit signed immediate for arith instructions with r0/r1/r2/r3 source"
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT)ival + 0x200000 < 0x400000")))
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(define_constraint "j"
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"(2**32-2**13)..(2**32-1) for addp4 instructions"
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT)ival >= 0xffffe000
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&& (unsigned HOST_WIDE_INT)ival <= 0xffffffff")))
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(define_constraint "K"
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"8 bit signed immediate for logical instructions"
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT)ival + 0x80 < 0x100")))
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(define_constraint "L"
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"8 bit adjusted signed immediate for compare pseudo-ops"
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT)ival + 0x7F < 0x100")))
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(define_constraint "M"
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"6 bit unsigned immediate for shift counts"
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT)ival < 0x40")))
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(define_constraint "N"
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"9 bit signed immediate for load/store post-increments"
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT)ival + 0x100 < 0x200")))
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(define_constraint "O"
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"constant zero"
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(and (match_code "const_int")
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(match_test "ival == 0")))
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(define_constraint "P"
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"0 or -1 for dep instruction"
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(and (match_code "const_int")
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(match_test "ival == 0 || ival == -1")))
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;; Floating-point constraints
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(define_constraint "G"
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"0.0 and 1.0 for fr0 and fr1"
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(and (match_code "const_double")
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(match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)")))
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(define_constraint "H"
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"0.0"
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(and (match_code "const_double")
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(match_test "op == CONST0_RTX (mode)")))
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;; Extra constraints
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;; Note that while this accepts mem, it only accepts non-volatile mem,
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;; and so cannot be "fixed" by adjusting the address. Thus it cannot
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;; and does not use define_memory_constraint.
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(define_constraint "Q"
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"Non-volatile memory for FP_REG loads/stores"
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(and (match_operand 0 "memory_operand")
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(match_test "!MEM_VOLATILE_P (op)")))
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(define_constraint "R"
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"1..4 for shladd arguments"
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(and (match_code "const_int")
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(match_test "ival >= 1 && ival <= 4")))
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(define_constraint "T"
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"Symbol ref to small-address-area"
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(match_operand 0 "small_addr_symbolic_operand"))
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(define_constraint "U"
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"vector zero constant"
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(and (match_code "const_vector")
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(match_test "op == CONST0_RTX (mode)")))
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(define_constraint "W"
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"An integer vector, such that conversion to an integer yields a
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value appropriate for an integer 'J' constraint."
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(and (match_code "const_vector")
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(match_test "GET_MODE_CLASS (mode) == MODE_VECTOR_INT")
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(match_test
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"satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
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(define_constraint "Y"
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"A V2SF vector containing elements that satisfy 'G'"
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(and (match_code "const_vector")
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(match_test "mode == V2SFmode")
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(match_test "satisfies_constraint_G (XVECEXP (op, 0, 0))")
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(match_test "satisfies_constraint_G (XVECEXP (op, 0, 1))")))
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;; Memory constraints
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(define_memory_constraint "S"
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"Non-post-inc memory for asms and other unsavory creatures"
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(and (match_code "mem")
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(match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
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