307 lines
11 KiB
Markdown
307 lines
11 KiB
Markdown
;; Pentium Scheduling
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;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>. */
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;;
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;; The Pentium is an in-order core with two integer pipelines.
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;; True for insns that behave like prefixed insns on the Pentium.
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(define_attr "pent_prefix" "false,true"
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(if_then_else (ior (eq_attr "prefix_0f" "1")
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(ior (eq_attr "prefix_data16" "1")
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(eq_attr "prefix_rep" "1")))
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(const_string "true")
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(const_string "false")))
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;; Categorize how an instruction slots.
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;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
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;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
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;; rules, because it results in noticeably better code on non-MMX Pentium
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;; and doesn't hurt much on MMX. (Prefixed instructions are not very
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;; common, so the scheduler usually has a non-prefixed insn to pair).
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(define_attr "pent_pair" "uv,pu,pv,np"
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(cond [(eq_attr "imm_disp" "true")
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(const_string "np")
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(ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
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(and (eq_attr "type" "pop,push")
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(eq_attr "memory" "!both")))
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(if_then_else (eq_attr "pent_prefix" "true")
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(const_string "pu")
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(const_string "uv"))
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(eq_attr "type" "ibr")
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(const_string "pv")
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(and (eq_attr "type" "ishift")
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(match_operand 2 "const_int_operand" ""))
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(const_string "pu")
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(and (eq_attr "type" "rotate")
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(match_operand 2 "const1_operand" ""))
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(const_string "pu")
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(and (eq_attr "type" "ishift1")
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(match_operand 1 "const_int_operand" ""))
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(const_string "pu")
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(and (eq_attr "type" "rotate1")
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(match_operand 1 "const1_operand" ""))
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(const_string "pu")
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(and (eq_attr "type" "call")
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(match_operand 0 "constant_call_address_operand" ""))
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(const_string "pv")
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(and (eq_attr "type" "callv")
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(match_operand 1 "constant_call_address_operand" ""))
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(const_string "pv")
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]
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(const_string "np")))
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(define_automaton "pentium,pentium_fpu")
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;; Pentium do have U and V pipes. Instruction to both pipes
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;; are always issued together, much like on VLIW.
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;;
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;; predecode
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;; / \
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;; decodeu decodev
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;; / | |
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;; fpu executeu executev
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;; | | |
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;; fpu retire retire
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;; |
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;; fpu
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;; We add dummy "port" pipes allocated only first cycle of
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;; instruction to specify this behavior.
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(define_cpu_unit "pentium-portu,pentium-portv" "pentium")
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(define_cpu_unit "pentium-u,pentium-v" "pentium")
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(absence_set "pentium-portu" "pentium-u,pentium-v")
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(presence_set "pentium-portv" "pentium-portu")
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;; Floating point instructions can overlap with new issue of integer
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;; instructions. We model only first cycle of FP pipeline, as it is
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;; fully pipelined.
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(define_cpu_unit "pentium-fp" "pentium_fpu")
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;; There is non-pipelined multiplier unit used for complex operations.
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(define_cpu_unit "pentium-fmul" "pentium_fpu")
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;; Pentium preserves memory ordering, so when load-execute-store
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;; instruction is executed together with other instruction loading
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;; data, the execution of the other instruction is delayed to very
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;; last cycle of first instruction, when data are bypassed.
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;; We model this by allocating "memory" unit when store is pending
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;; and using conflicting load units together.
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(define_cpu_unit "pentium-memory" "pentium")
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(define_cpu_unit "pentium-load0" "pentium")
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(define_cpu_unit "pentium-load1" "pentium")
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(absence_set "pentium-load0,pentium-load1" "pentium-memory")
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(define_reservation "pentium-load" "(pentium-load0 | pentium-load1)")
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(define_reservation "pentium-np" "(pentium-u + pentium-v)")
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(define_reservation "pentium-uv" "(pentium-u | pentium-v)")
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(define_reservation "pentium-portuv" "(pentium-portu | pentium-portv)")
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(define_reservation "pentium-firstu" "(pentium-u + pentium-portu)")
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(define_reservation "pentium-firstv" "(pentium-v + pentium-portuv)")
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(define_reservation "pentium-firstuv" "(pentium-uv + pentium-portuv)")
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(define_reservation "pentium-firstuload" "(pentium-load + pentium-firstu)")
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(define_reservation "pentium-firstvload" "(pentium-load + pentium-firstv)")
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(define_reservation "pentium-firstuvload" "(pentium-load + pentium-firstuv)
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| (pentium-firstv,pentium-v,
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(pentium-load+pentium-firstv))")
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(define_reservation "pentium-firstuboth" "(pentium-load + pentium-firstu
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+ pentium-memory)")
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(define_reservation "pentium-firstvboth" "(pentium-load + pentium-firstv
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+ pentium-memory)")
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(define_reservation "pentium-firstuvboth" "(pentium-load + pentium-firstuv
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+ pentium-memory)
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| (pentium-firstv,pentium-v,
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(pentium-load+pentium-firstv))")
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;; Few common long latency instructions
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(define_insn_reservation "pent_mul" 11
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "imul"))
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"pentium-np*11")
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(define_insn_reservation "pent_str" 12
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "str"))
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"pentium-np*12")
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;; Integer division and some other long latency instruction block all
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;; units, including the FP pipe. There is no value in modeling the
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;; latency of these instructions and not modeling the latency
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;; decreases the size of the DFA.
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(define_insn_reservation "pent_block" 1
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "idiv"))
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"pentium-np+pentium-fp")
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;; Moves usually have one cycle penalty, but there are exceptions.
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(define_insn_reservation "pent_fmov" 1
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "type" "fmov")
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(eq_attr "memory" "none,load")))
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"(pentium-fp+pentium-np)")
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(define_insn_reservation "pent_fpmovxf" 3
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "type" "fmov")
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(and (eq_attr "memory" "load,store")
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(eq_attr "mode" "XF"))))
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"(pentium-fp+pentium-np)*3")
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(define_insn_reservation "pent_fpstore" 2
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "type" "fmov")
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(ior (match_operand 1 "immediate_operand" "")
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(eq_attr "memory" "store"))))
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"(pentium-fp+pentium-np)*2")
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(define_insn_reservation "pent_imov" 1
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "imov"))
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"pentium-firstuv")
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;; Push and pop instructions have 1 cycle latency and special
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;; hardware bypass allows them to be paired with other push,pop
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;; and call instructions.
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(define_bypass 0 "pent_push,pent_pop" "pent_push,pent_pop,pent_call")
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(define_insn_reservation "pent_push" 1
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "type" "push")
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(eq_attr "memory" "store")))
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"pentium-firstuv")
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(define_insn_reservation "pent_pop" 1
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "pop,leave"))
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"pentium-firstuv")
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;; Call and branch instruction can execute in either pipe, but
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;; they are only pairable when in the v pipe.
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(define_insn_reservation "pent_call" 10
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "call,callv"))
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"pentium-firstv,pentium-v*9")
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(define_insn_reservation "pent_branch" 1
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "ibr"))
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"pentium-firstv")
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;; Floating point instruction dispatch in U pipe, but continue
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;; in FP pipeline allowing other instructions to be executed.
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(define_insn_reservation "pent_fp" 3
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "fop,fistp"))
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"(pentium-firstu+pentium-fp),nothing,nothing")
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;; First two cycles of fmul are not pipelined.
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(define_insn_reservation "pent_fmul" 3
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "fmul"))
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"(pentium-firstuv+pentium-fp+pentium-fmul),pentium-fmul,nothing")
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;; Long latency FP instructions overlap with integer instructions,
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;; but only last 2 cycles with FP ones.
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(define_insn_reservation "pent_fdiv" 39
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "fdiv"))
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"(pentium-np+pentium-fp+pentium-fmul),
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(pentium-fp+pentium-fmul)*36,pentium-fmul*2")
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(define_insn_reservation "pent_fpspc" 70
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(and (eq_attr "cpu" "pentium")
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(eq_attr "type" "fpspc"))
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"(pentium-np+pentium-fp+pentium-fmul),
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(pentium-fp+pentium-fmul)*67,pentium-fmul*2")
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;; Integer instructions. Load/execute/store takes 3 cycles,
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;; load/execute 2 cycles and execute only one cycle.
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(define_insn_reservation "pent_uv_both" 3
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "uv")
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(eq_attr "memory" "both")))
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"pentium-firstuvboth,pentium-uv+pentium-memory,pentium-uv")
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(define_insn_reservation "pent_u_both" 3
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "pu")
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(eq_attr "memory" "both")))
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"pentium-firstuboth,pentium-u+pentium-memory,pentium-u")
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(define_insn_reservation "pent_v_both" 3
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "pv")
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(eq_attr "memory" "both")))
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"pentium-firstvboth,pentium-v+pentium-memory,pentium-v")
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(define_insn_reservation "pent_np_both" 3
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "np")
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(eq_attr "memory" "both")))
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"pentium-np,pentium-np,pentium-np")
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(define_insn_reservation "pent_uv_load" 2
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "uv")
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(eq_attr "memory" "load")))
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"pentium-firstuvload,pentium-uv")
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(define_insn_reservation "pent_u_load" 2
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "pu")
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(eq_attr "memory" "load")))
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"pentium-firstuload,pentium-u")
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(define_insn_reservation "pent_v_load" 2
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "pv")
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(eq_attr "memory" "load")))
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"pentium-firstvload,pentium-v")
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(define_insn_reservation "pent_np_load" 2
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "np")
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(eq_attr "memory" "load")))
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"pentium-np,pentium-np")
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(define_insn_reservation "pent_uv" 1
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "uv")
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(eq_attr "memory" "none")))
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"pentium-firstuv")
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(define_insn_reservation "pent_u" 1
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "pu")
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(eq_attr "memory" "none")))
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"pentium-firstu")
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(define_insn_reservation "pent_v" 1
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "pv")
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(eq_attr "memory" "none")))
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"pentium-firstv")
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(define_insn_reservation "pent_np" 1
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(and (eq_attr "cpu" "pentium")
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(and (eq_attr "pent_pair" "np")
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(eq_attr "memory" "none")))
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"pentium-np")
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