541 lines
20 KiB
Markdown
541 lines
20 KiB
Markdown
;; Cirrus EP9312 "Maverick" ARM floating point co-processor description.
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;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;; Written by Aldy Hernandez (aldyh@redhat.com)
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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; Cirrus types for invalid insn combinations
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; not Not a cirrus insn
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; normal Any Cirrus insn not covered by the special cases below
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; double cfldrd, cfldr64, cfstrd, cfstr64
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; compare cfcmps, cfcmpd, cfcmp32, cfcmp64
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; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr
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(define_attr "cirrus" "not,normal,double,compare,move" (const_string "not"))
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(define_insn "cirrus_adddi3"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(plus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:DI 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfadd64%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_addsi3"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(plus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfadd32%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_addsf3"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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(match_operand:SF 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfadds%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_adddf3"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(plus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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(match_operand:DF 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfaddd%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "cirrus_subdi3"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(minus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:DI 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfsub64%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_subsi3_insn"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(minus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfsub32%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_subsf3"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(minus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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(match_operand:SF 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfsubs%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_subdf3"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(minus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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(match_operand:DF 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfsubd%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_mulsi3"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
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(match_operand:SI 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfmul32%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "muldi3"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(mult:DI (match_operand:DI 2 "cirrus_fp_register" "v")
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(match_operand:DI 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfmul64%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_dmult")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_mulsi3addsi"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(plus:SI
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(mult:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_fp_register" "v"))
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(match_operand:SI 3 "cirrus_fp_register" "0")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfmac32%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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;; Cirrus SI multiply-subtract
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(define_insn "*cirrus_mulsi3subsi"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(minus:SI
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(match_operand:SI 1 "cirrus_fp_register" "0")
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(mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
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(match_operand:SI 3 "cirrus_fp_register" "v"))))]
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"0 && TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfmsc32%?\\t%V0, %V2, %V3"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_mulsf3"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(mult:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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(match_operand:SF 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfmuls%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_farith")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_muldf3"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(mult:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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(match_operand:DF 2 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfmuld%?\\t%V0, %V1, %V2"
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[(set_attr "type" "mav_dmult")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "cirrus_ashl_const"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_shift_const" "")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfsh32%?\\t%V0, %V1, #%s2"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "cirrus_ashiftrt_const"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_shift_const" "")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfsh32%?\\t%V0, %V1, #-%s2"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "cirrus_ashlsi3"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfrshl32%?\\t%V1, %V0, %s2"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "ashldi3_cirrus"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfrshl64%?\\t%V1, %V0, %s2"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "cirrus_ashldi_const"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_shift_const" "")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfsh64%?\\t%V0, %V1, #%s2"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "cirrus_ashiftrtdi_const"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_shift_const" "")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfsh64%?\\t%V0, %V1, #-%s2"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_absdi2"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfabs64%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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;; This doesn't really clobber ``cc''. Fixme: aldyh.
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(define_insn "*cirrus_negdi2"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(neg:DI (match_operand:DI 1 "cirrus_fp_register" "v")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfneg64%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_negsi2"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfneg32%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_negsf2"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfnegs%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_negdf2"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfnegd%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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;; This doesn't really clobber the condition codes either.
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(define_insn "*cirrus_abssi2"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(abs:SI (match_operand:SI 1 "cirrus_fp_register" "v")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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"cfabs32%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_abssf2"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfabss%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_absdf2"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfabsd%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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;; Convert Cirrus-SI to Cirrus-SF
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(define_insn "cirrus_floatsisf2"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(float:SF (match_operand:SI 1 "s_register_operand" "r")))
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(clobber (match_scratch:DF 2 "=v"))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
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[(set_attr "length" "8")
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(set_attr "cirrus" "move")]
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)
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(define_insn "cirrus_floatsidf2"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(float:DF (match_operand:SI 1 "s_register_operand" "r")))
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(clobber (match_scratch:DF 2 "=v"))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
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[(set_attr "length" "8")
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(set_attr "cirrus" "move")]
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)
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(define_insn "floatdisf2"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfcvt64s%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")])
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(define_insn "floatdidf2"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfcvt64d%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")])
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(define_insn "cirrus_truncsfsi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
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(clobber (match_scratch:DF 2 "=v"))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
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[(set_attr "length" "8")
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(set_attr "cirrus" "normal")]
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)
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(define_insn "cirrus_truncdfsi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v"))))
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(clobber (match_scratch:DF 2 "=v"))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
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[(set_attr "length" "8")]
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)
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(define_insn "*cirrus_truncdfsf2"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(float_truncate:SF
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(match_operand:DF 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfcvtds%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_extendsfdf2"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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"cfcvtsd%?\\t%V0, %V1"
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[(set_attr "cirrus" "normal")]
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)
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(define_insn "*cirrus_arm_movdi"
|
||
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
|
||
(match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
|
||
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
|
||
"*
|
||
{
|
||
switch (which_alternative)
|
||
{
|
||
case 0:
|
||
return \"#\";
|
||
case 1:
|
||
case 2:
|
||
return output_move_double (operands);
|
||
|
||
case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
|
||
case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
|
||
|
||
case 5: return \"cfldr64%?\\t%V0, %1\";
|
||
case 6: return \"cfstr64%?\\t%V1, %0\";
|
||
|
||
/* Shifting by 0 will just copy %1 into %0. */
|
||
case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
|
||
|
||
default: gcc_unreachable ();
|
||
}
|
||
}"
|
||
[(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
|
||
(set_attr "type" " *,load2,store2, *, *, load2,store2, *")
|
||
(set_attr "pool_range" " *,1020, *, *, *, 1020, *, *")
|
||
(set_attr "neg_pool_range" " *,1012, *, *, *, 1008, *, *")
|
||
(set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
|
||
)
|
||
|
||
;; Cirrus SI values have been outlawed. Look in arm.h for the comment
|
||
;; on HARD_REGNO_MODE_OK.
|
||
|
||
(define_insn "*cirrus_movsf_hard_insn"
|
||
[(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
|
||
(match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
|
||
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK
|
||
&& (GET_CODE (operands[0]) != MEM
|
||
|| register_operand (operands[1], SFmode))"
|
||
"@
|
||
cfcpys%?\\t%V0, %V1
|
||
cfldrs%?\\t%V0, %1
|
||
cfmvsr%?\\t%V0, %1
|
||
cfmvrs%?\\t%0, %V1
|
||
cfstrs%?\\t%V1, %0
|
||
mov%?\\t%0, %1
|
||
ldr%?\\t%0, %1\\t%@ float
|
||
str%?\\t%1, %0\\t%@ float"
|
||
[(set_attr "length" " *, *, *, *, *, 4, 4, 4")
|
||
(set_attr "type" " *, load1, *, *,store1, *,load1,store1")
|
||
(set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
|
||
(set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *")
|
||
(set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
|
||
)
|
||
|
||
(define_insn "*cirrus_movdf_hard_insn"
|
||
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
|
||
(match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
|
||
"TARGET_ARM
|
||
&& TARGET_HARD_FLOAT && TARGET_MAVERICK
|
||
&& (GET_CODE (operands[0]) != MEM
|
||
|| register_operand (operands[1], DFmode))"
|
||
"*
|
||
{
|
||
switch (which_alternative)
|
||
{
|
||
case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
|
||
case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
|
||
case 2: return \"#\";
|
||
case 3: case 4: return output_move_double (operands);
|
||
case 5: return \"cfcpyd%?\\t%V0, %V1\";
|
||
case 6: return \"cfldrd%?\\t%V0, %1\";
|
||
case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
|
||
case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
|
||
case 9: return \"cfstrd%?\\t%V1, %0\";
|
||
default: gcc_unreachable ();
|
||
}
|
||
}"
|
||
[(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
|
||
(set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
|
||
(set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *")
|
||
(set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *")
|
||
(set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
|
||
)
|
||
|
||
(define_insn "*cirrus_thumb2_movdi"
|
||
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
|
||
(match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
|
||
"TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK"
|
||
"*
|
||
{
|
||
switch (which_alternative)
|
||
{
|
||
case 0:
|
||
case 1:
|
||
case 2:
|
||
return (output_move_double (operands));
|
||
|
||
case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
|
||
case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
|
||
|
||
case 5: return \"cfldr64%?\\t%V0, %1\";
|
||
case 6: return \"cfstr64%?\\t%V1, %0\";
|
||
|
||
/* Shifting by 0 will just copy %1 into %0. */
|
||
case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
|
||
|
||
default: abort ();
|
||
}
|
||
}"
|
||
[(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
|
||
(set_attr "type" " *,load2,store2, *, *, load2,store2, *")
|
||
(set_attr "pool_range" " *,4096, *, *, *, 1020, *, *")
|
||
(set_attr "neg_pool_range" " *, 0, *, *, *, 1008, *, *")
|
||
(set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
|
||
)
|
||
|
||
(define_insn "*thumb2_cirrus_movsf_hard_insn"
|
||
[(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
|
||
(match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
|
||
"TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK
|
||
&& (GET_CODE (operands[0]) != MEM
|
||
|| register_operand (operands[1], SFmode))"
|
||
"@
|
||
cfcpys%?\\t%V0, %V1
|
||
cfldrs%?\\t%V0, %1
|
||
cfmvsr%?\\t%V0, %1
|
||
cfmvrs%?\\t%0, %V1
|
||
cfstrs%?\\t%V1, %0
|
||
mov%?\\t%0, %1
|
||
ldr%?\\t%0, %1\\t%@ float
|
||
str%?\\t%1, %0\\t%@ float"
|
||
[(set_attr "length" " *, *, *, *, *, 4, 4, 4")
|
||
(set_attr "type" " *, load1, *, *,store1, *,load1,store1")
|
||
(set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
|
||
(set_attr "neg_pool_range" " *, 1008, *, *, *, *, 0, *")
|
||
(set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
|
||
)
|
||
|
||
(define_insn "*thumb2_cirrus_movdf_hard_insn"
|
||
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
|
||
(match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
|
||
"TARGET_THUMB2
|
||
&& TARGET_HARD_FLOAT && TARGET_MAVERICK
|
||
&& (GET_CODE (operands[0]) != MEM
|
||
|| register_operand (operands[1], DFmode))"
|
||
"*
|
||
{
|
||
switch (which_alternative)
|
||
{
|
||
case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
|
||
case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
|
||
case 2: case 3: case 4: return output_move_double (operands);
|
||
case 5: return \"cfcpyd%?\\t%V0, %V1\";
|
||
case 6: return \"cfldrd%?\\t%V0, %1\";
|
||
case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
|
||
case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
|
||
case 9: return \"cfstrd%?\\t%V1, %0\";
|
||
default: abort ();
|
||
}
|
||
}"
|
||
[(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
|
||
(set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
|
||
(set_attr "pool_range" " *, *, *, *,4092, *, 1020, *, *, *")
|
||
(set_attr "neg_pool_range" " *, *, *, *, 0, *, 1008, *, *, *")
|
||
(set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
|
||
)
|
||
|