188 lines
6.1 KiB
Markdown
188 lines
6.1 KiB
Markdown
;; ARM 926EJ-S Pipeline Description
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;; Copyright (C) 2003, 2007 Free Software Foundation, Inc.
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;; Written by CodeSourcery, LLC.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>. */
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;; These descriptions are based on the information contained in the
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;; ARM926EJ-S Technical Reference Manual, Copyright (c) 2002 ARM
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;; Limited.
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;;
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;; This automaton provides a pipeline description for the ARM
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;; 926EJ-S core.
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;;
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;; The model given here assumes that the condition for all conditional
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;; instructions is "true", i.e., that all of the instructions are
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;; actually executed.
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(define_automaton "arm926ejs")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Pipelines
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; There is a single pipeline
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;;
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;; The ALU pipeline has fetch, decode, execute, memory, and
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;; write stages. We only need to model the execute, memory and write
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;; stages.
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(define_cpu_unit "e,m,w" "arm926ejs")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU instructions require three cycles to execute, and use the ALU
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;; pipeline in each of the three stages. The results are available
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;; after the execute stage stage has finished.
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;;
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;; If the destination register is the PC, the pipelines are stalled
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;; for several cycles. That case is not modeled here.
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;; ALU operations with no shifted operand
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(define_insn_reservation "9_alu_op" 1
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "alu,alu_shift"))
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"e,m,w")
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;; ALU operations with a shift-by-register operand
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;; These really stall in the decoder, in order to read
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;; the shift value in a second cycle. Pretend we take two cycles in
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;; the execute stage.
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(define_insn_reservation "9_alu_shift_reg_op" 2
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "alu_shift_reg"))
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"e*2,m,w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication instructions loop in the execute stage until the
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;; instruction has been passed through the multiplier array enough
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;; times. Multiply operations occur in both the execute and memory
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;; stages of the pipeline
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(define_insn_reservation "9_mult1" 3
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "insn" "smlalxy,mul,mla"))
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"e*2,m,w")
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(define_insn_reservation "9_mult2" 4
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "insn" "muls,mlas"))
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"e*3,m,w")
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(define_insn_reservation "9_mult3" 4
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "insn" "umull,umlal,smull,smlal"))
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"e*3,m,w")
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(define_insn_reservation "9_mult4" 5
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "insn" "umulls,umlals,smulls,smlals"))
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"e*4,m,w")
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(define_insn_reservation "9_mult5" 2
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "insn" "smulxy,smlaxy,smlawx"))
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"e,m,w")
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(define_insn_reservation "9_mult6" 3
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "insn" "smlalxy"))
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"e*2,m,w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Load/Store Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The models for load/store instructions do not accurately describe
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;; the difference between operations with a base register writeback
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;; (such as "ldm!"). These models assume that all memory references
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;; hit in dcache.
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;; Loads with a shifted offset take 3 cycles, and are (a) probably the
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;; most common and (b) the pessimistic assumption will lead to fewer stalls.
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(define_insn_reservation "9_load1_op" 3
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "load1,load_byte"))
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"e*2,m,w")
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(define_insn_reservation "9_store1_op" 0
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "store1"))
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"e,m,w")
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;; multiple word loads and stores
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(define_insn_reservation "9_load2_op" 3
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "load2"))
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"e,m*2,w")
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(define_insn_reservation "9_load3_op" 4
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "load3"))
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"e,m*3,w")
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(define_insn_reservation "9_load4_op" 5
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "load4"))
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"e,m*4,w")
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(define_insn_reservation "9_store2_op" 0
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "store2"))
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"e,m*2,w")
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(define_insn_reservation "9_store3_op" 0
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "store3"))
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"e,m*3,w")
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(define_insn_reservation "9_store4_op" 0
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "store4"))
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"e,m*4,w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch and Call Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch instructions are difficult to model accurately. The ARM
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;; core can predict most branches. If the branch is predicted
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;; correctly, and predicted early enough, the branch can be completely
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;; eliminated from the instruction stream. Some branches can
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;; therefore appear to require zero cycles to execute. We assume that
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;; all branches are predicted correctly, and that the latency is
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;; therefore the minimum value.
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(define_insn_reservation "9_branch_op" 0
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "branch"))
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"nothing")
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;; The latency for a call is not predictable. Therefore, we use 32 as
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;; roughly equivalent to positive infinity.
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(define_insn_reservation "9_call_op" 32
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(and (eq_attr "tune" "arm926ejs")
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(eq_attr "type" "call"))
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"nothing")
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