207 lines
6.4 KiB
C
207 lines
6.4 KiB
C
#define _FP_W_TYPE_SIZE 32
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#define _FP_W_TYPE unsigned int
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#define _FP_WS_TYPE signed int
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#define _FP_I_TYPE int
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/* The type of the result of a floating point comparison. This must
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match `__libgcc_cmp_return__' in GCC for the target. */
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typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
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#define CMPtype __gcc_CMPtype
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#define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
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__asm__ ("add{l} {%11,%3|%3,%11}\n\t" \
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"adc{l} {%9,%2|%2,%9}\n\t" \
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"adc{l} {%7,%1|%1,%7}\n\t" \
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"adc{l} {%5,%0|%0,%5}" \
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: "=r" ((USItype) (r3)), \
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"=&r" ((USItype) (r2)), \
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"=&r" ((USItype) (r1)), \
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"=&r" ((USItype) (r0)) \
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: "%0" ((USItype) (x3)), \
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"g" ((USItype) (y3)), \
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"%1" ((USItype) (x2)), \
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"g" ((USItype) (y2)), \
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"%2" ((USItype) (x1)), \
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"g" ((USItype) (y1)), \
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"%3" ((USItype) (x0)), \
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"g" ((USItype) (y0)))
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#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
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__asm__ ("add{l} {%8,%2|%2,%8}\n\t" \
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"adc{l} {%6,%1|%1,%6}\n\t" \
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"adc{l} {%4,%0|%0,%4}" \
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: "=r" ((USItype) (r2)), \
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"=&r" ((USItype) (r1)), \
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"=&r" ((USItype) (r0)) \
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: "%0" ((USItype) (x2)), \
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"g" ((USItype) (y2)), \
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"%1" ((USItype) (x1)), \
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"g" ((USItype) (y1)), \
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"%2" ((USItype) (x0)), \
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"g" ((USItype) (y0)))
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#define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
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__asm__ ("sub{l} {%11,%3|%3,%11}\n\t" \
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"sbb{l} {%9,%2|%2,%9}\n\t" \
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"sbb{l} {%7,%1|%1,%7}\n\t" \
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"sbb{l} {%5,%0|%0,%5}" \
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: "=r" ((USItype) (r3)), \
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"=&r" ((USItype) (r2)), \
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"=&r" ((USItype) (r1)), \
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"=&r" ((USItype) (r0)) \
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: "0" ((USItype) (x3)), \
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"g" ((USItype) (y3)), \
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"1" ((USItype) (x2)), \
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"g" ((USItype) (y2)), \
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"2" ((USItype) (x1)), \
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"g" ((USItype) (y1)), \
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"3" ((USItype) (x0)), \
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"g" ((USItype) (y0)))
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#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
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__asm__ ("sub{l} {%8,%2|%2,%8}\n\t" \
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"sbb{l} {%6,%1|%1,%6}\n\t" \
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"sbb{l} {%4,%0|%0,%4}" \
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: "=r" ((USItype) (r2)), \
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"=&r" ((USItype) (r1)), \
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"=&r" ((USItype) (r0)) \
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: "0" ((USItype) (x2)), \
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"g" ((USItype) (y2)), \
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"1" ((USItype) (x1)), \
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"g" ((USItype) (y1)), \
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"2" ((USItype) (x0)), \
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"g" ((USItype) (y0)))
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#define _FP_MUL_MEAT_Q(R,X,Y) \
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_FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
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#define _FP_NANFRAC_S _FP_QNANBIT_S
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#define _FP_NANFRAC_D _FP_QNANBIT_D, 0
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/* Even if XFmode is 12byte, we have to pad it to
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16byte since soft-fp emulation is done in 16byte. */
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#define _FP_NANFRAC_E _FP_QNANBIT_E, 0, 0, 0
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#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
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#define _FP_NANSIGN_S 1
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#define _FP_NANSIGN_D 1
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#define _FP_NANSIGN_E 1
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#define _FP_NANSIGN_Q 1
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#define _FP_KEEPNANFRACP 1
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/* Here is something Intel misdesigned: the specs don't define
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the case where we have two NaNs with same mantissas, but
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different sign. Different operations pick up different NaNs. */
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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if (_FP_FRAC_GT_##wc(X, Y) \
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|| (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
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{ \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R,X); \
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} \
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else \
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{ \
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R##_s = Y##_s; \
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_FP_FRAC_COPY_##wc(R,Y); \
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} \
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R##_c = FP_CLS_NAN; \
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} while (0)
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#define FP_EX_INVALID 0x01
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#define FP_EX_DENORM 0x02
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#define FP_EX_DIVZERO 0x04
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#define FP_EX_OVERFLOW 0x08
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#define FP_EX_UNDERFLOW 0x10
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#define FP_EX_INEXACT 0x20
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struct fenv
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{
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unsigned short int __control_word;
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unsigned short int __unused1;
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unsigned short int __status_word;
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unsigned short int __unused2;
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unsigned short int __tags;
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unsigned short int __unused3;
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unsigned int __eip;
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unsigned short int __cs_selector;
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unsigned int __opcode:11;
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unsigned int __unused4:5;
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unsigned int __data_offset;
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unsigned short int __data_selector;
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unsigned short int __unused5;
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};
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#define FP_HANDLE_EXCEPTIONS \
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do { \
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if (_fex & FP_EX_INVALID) \
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{ \
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float f = 0.0; \
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__asm__ __volatile__ ("fdiv {%y0, %0|%0, %y0}" : "+t" (f)); \
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__asm__ __volatile__ ("fwait"); \
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} \
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if (_fex & FP_EX_DIVZERO) \
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{ \
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float f = 1.0, g = 0.0; \
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__asm__ __volatile__ ("fdivp" : "=t" (f) \
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: "0" (f), "u" (g) \
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: "st(1)"); \
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__asm__ __volatile__ ("fwait"); \
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} \
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if (_fex & FP_EX_OVERFLOW) \
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{ \
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struct fenv temp; \
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__asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
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temp.__status_word |= FP_EX_OVERFLOW; \
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__asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
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__asm__ __volatile__ ("fwait"); \
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} \
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if (_fex & FP_EX_UNDERFLOW) \
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{ \
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struct fenv temp; \
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__asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
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temp.__status_word |= FP_EX_UNDERFLOW; \
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__asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
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__asm__ __volatile__ ("fwait"); \
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} \
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if (_fex & FP_EX_INEXACT) \
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{ \
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struct fenv temp; \
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__asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
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temp.__status_word |= FP_EX_INEXACT; \
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__asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
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__asm__ __volatile__ ("fwait"); \
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} \
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} while (0)
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#define FP_RND_NEAREST 0
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#define FP_RND_ZERO 0xc00
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#define FP_RND_PINF 0x800
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#define FP_RND_MINF 0x400
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#define _FP_DECL_EX \
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unsigned short _fcw __attribute__ ((unused)) = FP_RND_NEAREST
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#define FP_INIT_ROUNDMODE \
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do { \
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__asm__ ("fnstcw %0" : "=m" (_fcw)); \
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} while (0)
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#define FP_ROUNDMODE (_fcw & 0xc00)
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#define __LITTLE_ENDIAN 1234
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#define __BIG_ENDIAN 4321
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#define __BYTE_ORDER __LITTLE_ENDIAN
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/* Define ALIASNAME as a strong alias for NAME. */
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#if defined __MACH__
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/* Mach-O doesn't support aliasing. If these functions ever return
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anything but CMPtype we need to revisit this... */
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#define strong_alias(name, aliasname) \
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CMPtype aliasname (TFtype a, TFtype b) { return name(a, b); }
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#else
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# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
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# define _strong_alias(name, aliasname) \
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extern __typeof (name) aliasname __attribute__ ((alias (#name)));
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#endif
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