341 lines
8.8 KiB
Plaintext
341 lines
8.8 KiB
Plaintext
; Options for the rs6000 port of the compiler
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;
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; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
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; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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; License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; <http://www.gnu.org/licenses/>.
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mpower
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Target Report RejectNegative Mask(POWER)
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Use POWER instruction set
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mno-power
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Target Report RejectNegative
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Do not use POWER instruction set
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mpower2
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Target Report Mask(POWER2)
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Use POWER2 instruction set
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mpowerpc
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Target Report RejectNegative Mask(POWERPC)
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Use PowerPC instruction set
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mno-powerpc
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Target Report RejectNegative
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Do not use PowerPC instruction set
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mpowerpc64
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Target Report Mask(POWERPC64)
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Use PowerPC-64 instruction set
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mpowerpc-gpopt
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Target Report Mask(PPC_GPOPT)
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Use PowerPC General Purpose group optional instructions
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mpowerpc-gfxopt
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Target Report Mask(PPC_GFXOPT)
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Use PowerPC Graphics group optional instructions
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mmfcrf
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Target Report Mask(MFCRF)
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Use PowerPC V2.01 single field mfcr instruction
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mpopcntb
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Target Report Mask(POPCNTB)
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Use PowerPC V2.02 popcntb instruction
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mfprnd
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Target Report Mask(FPRND)
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Use PowerPC V2.02 floating point rounding instructions
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mcmpb
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Target Report Mask(CMPB)
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Use PowerPC V2.05 compare bytes instruction
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mmfpgpr
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Target Report Mask(MFPGPR)
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Use extended PowerPC V2.05 move floating point to/from GPR instructions
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maltivec
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Target Report Mask(ALTIVEC)
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Use AltiVec instructions
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mhard-dfp
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Target Report Mask(DFP)
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Use decimal floating point instructions
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mmulhw
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Target Report Mask(MULHW)
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Use 4xx half-word multiply instructions
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mdlmzb
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Target Report Mask(DLMZB)
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Use 4xx string-search dlmzb instruction
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mmultiple
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Target Report Mask(MULTIPLE)
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Generate load/store multiple instructions
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mstring
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Target Report Mask(STRING)
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Generate string instructions for block moves
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mnew-mnemonics
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Target Report RejectNegative Mask(NEW_MNEMONICS)
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Use new mnemonics for PowerPC architecture
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mold-mnemonics
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Target Report RejectNegative InverseMask(NEW_MNEMONICS)
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Use old mnemonics for PowerPC architecture
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msoft-float
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Target Report RejectNegative Mask(SOFT_FLOAT)
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Do not use hardware floating point
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mhard-float
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Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
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Use hardware floating point
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mpopcntd
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Target Report Mask(POPCNTD)
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Use PowerPC V2.06 popcntd instruction
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mvsx
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Target Report Mask(VSX)
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Use vector/scalar (VSX) instructions
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mvsx-scalar-double
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Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)
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; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)
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mvsx-scalar-memory
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Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)
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; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)
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mvsx-align-128
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Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
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; If -mvsx, set alignment to 128 bits instead of 32/64
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mallow-movmisalign
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Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
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; Allow/disallow the movmisalign in DF/DI vectors
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mallow-df-permute
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Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
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; Allow/disallow permutation of DF/DI vectors
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msched-groups
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Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1)
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; Explicitly set/unset whether rs6000_sched_groups is set
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malways-hint
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Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1)
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; Explicitly set/unset whether rs6000_always_hint is set
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malign-branch-targets
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Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1)
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; Explicitly set/unset whether rs6000_align_branch_targets is set
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mvectorize-builtins
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Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1)
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; Explicitly control whether we vectorize the builtins or not.
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mno-update
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Target Report RejectNegative Mask(NO_UPDATE)
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Do not generate load/store with update instructions
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mupdate
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Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
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Generate load/store with update instructions
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mavoid-indexed-addresses
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Target Report Var(TARGET_AVOID_XFORM) Init(-1)
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Avoid generation of indexed load/store instructions when possible
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mfused-madd
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Target Report Var(TARGET_FUSED_MADD) Init(1)
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Generate fused multiply/add instructions
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mtls-markers
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Target Report Var(tls_markers) Init(1)
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Mark __tls_get_addr calls with argument info
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msched-epilog
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Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1)
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msched-prolog
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Target Report Var(TARGET_SCHED_PROLOG) VarExists
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Schedule the start and end of the procedure
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maix-struct-return
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Target Report RejectNegative Var(aix_struct_return)
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Return all structures in memory (AIX default)
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msvr4-struct-return
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Target Report RejectNegative Var(aix_struct_return,0) VarExists
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Return small structures in registers (SVR4 default)
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mxl-compat
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Target Report Var(TARGET_XL_COMPAT)
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Conform more closely to IBM XLC semantics
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mrecip
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Target Report Var(TARGET_RECIP)
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Generate software reciprocal sqrt for better throughput
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mno-fp-in-toc
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Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC)
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Do not place floating point constants in TOC
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mfp-in-toc
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Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0)
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Place floating point constants in TOC
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mno-sum-in-toc
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Target RejectNegative Var(TARGET_NO_SUM_IN_TOC)
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Do not place symbol+offset constants in TOC
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msum-in-toc
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Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) VarExists
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Place symbol+offset constants in TOC
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; Output only one TOC entry per module. Normally linking fails if
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; there are more than 16K unique variables/constants in an executable. With
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; this option, linking fails only if there are more than 16K modules, or
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; if there are more than 16K unique variables/constant in a single module.
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;
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; This is at the cost of having 2 extra loads and one extra store per
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; function, and one less allocable register.
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mminimal-toc
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Target Report Mask(MINIMAL_TOC)
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Use only one TOC entry per procedure
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mfull-toc
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Target Report
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Put everything in the regular TOC
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mvrsave
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Target Report Var(TARGET_ALTIVEC_VRSAVE)
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Generate VRSAVE instructions when generating AltiVec code
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mvrsave=
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Target RejectNegative Joined
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-mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead
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misel
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Target Report Mask(ISEL)
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Generate isel instructions
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misel=
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Target RejectNegative Joined
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-misel=yes/no Deprecated option. Use -misel/-mno-isel instead
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mspe
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Target
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Generate SPE SIMD instructions on E500
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mpaired
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Target Var(rs6000_paired_float)
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Generate PPC750CL paired-single instructions
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mspe=
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Target RejectNegative Joined
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-mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead
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mdebug=
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Target RejectNegative Joined
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-mdebug= Enable debug output
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mabi=
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Target RejectNegative Joined
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-mabi= Specify ABI to use
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mcpu=
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Target RejectNegative Joined
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-mcpu= Use features of and schedule code for given CPU
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mtune=
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Target RejectNegative Joined
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-mtune= Schedule code for given CPU
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mtraceback=
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Target RejectNegative Joined
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-mtraceback= Select full, part, or no traceback table
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mlongcall
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Target Report Var(rs6000_default_long_calls)
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Avoid all range limits on call instructions
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mgen-cell-microcode
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Target Report Var(rs6000_gen_cell_microcode) Init(-1)
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Generate Cell microcode
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mwarn-cell-microcode
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Target Var(rs6000_warn_cell_microcode) Init(0) Warning
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Warn when a Cell microcoded instruction is emitted
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mwarn-altivec-long
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Target Var(rs6000_warn_altivec_long) Init(1)
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Warn about deprecated 'vector long ...' AltiVec type usage
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mfloat-gprs=
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Target RejectNegative Joined
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-mfloat-gprs= Select GPR floating point method
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mlong-double-
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Target RejectNegative Joined UInteger
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-mlong-double-<n> Specify size of long double (64 or 128 bits)
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msched-costly-dep=
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Target RejectNegative Joined
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Determine which dependences between insns are considered costly
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minsert-sched-nops=
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Target RejectNegative Joined
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Specify which post scheduling nop insertion scheme to apply
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malign-
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Target RejectNegative Joined
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Specify alignment of structure fields default/natural
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mprioritize-restricted-insns=
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Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority)
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Specify scheduling priority for dispatch slot restricted insns
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msingle-float
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Target RejectNegative Var(rs6000_single_float)
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Single-precision floating point unit
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mdouble-float
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Target RejectNegative Var(rs6000_double_float)
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Double-precision floating point unit
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msimple-fpu
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Target RejectNegative Var(rs6000_simple_fpu)
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Floating point unit does not support divide & sqrt
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mfpu=
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Target RejectNegative Joined
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-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)
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mxilinx-fpu
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Target Var(rs6000_xilinx_fpu)
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Specify Xilinx FPU.
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