390 lines
15 KiB
C++
390 lines
15 KiB
C++
/* Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
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2008 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/* Standard register usage. */
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/* Number of actual hardware registers.
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The hardware registers are assigned numbers for the compiler
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from 0 to just below FIRST_PSEUDO_REGISTER.
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All registers that the compiler knows about must be given numbers,
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even those that are not normally considered general registers.
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HP-PA 1.0 has 32 fullword registers and 16 floating point
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registers. The floating point registers hold either word or double
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word values.
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16 additional registers are reserved.
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HP-PA 1.1 has 32 fullword registers and 32 floating point
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registers. However, the floating point registers behave
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differently: the left and right halves of registers are addressable
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as 32-bit registers. So, we will set things up like the 68k which
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has different fp units: define separate register sets for the 1.0
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and 1.1 fp units. */
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#define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs +
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+ 1 shift reg */
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator.
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On the HP-PA, these are:
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Reg 0 = 0 (hardware). However, 0 is used for condition code,
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so is not fixed.
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Reg 1 = ADDIL target/Temporary (hardware).
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Reg 2 = Return Pointer
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Reg 3 = Frame Pointer
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Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
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Reg 4-18 = Preserved Registers
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Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
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Reg 20-22 = Temporary Registers
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Reg 23-26 = Temporary/Parameter Registers
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Reg 27 = Global Data Pointer (hp)
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Reg 28 = Temporary/Return Value register
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Reg 29 = Temporary/Static Chain/Return Value register #2
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Reg 30 = stack pointer
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Reg 31 = Temporary/Millicode Return Pointer (hp)
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Freg 0-3 = Status Registers -- Not known to the compiler.
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Freg 4-7 = Arguments/Return Value
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Freg 8-11 = Temporary Registers
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Freg 12-15 = Preserved Registers
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Freg 16-31 = Reserved
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On the Snake, fp regs are
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Freg 0-3 = Status Registers -- Not known to the compiler.
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Freg 4L-7R = Arguments/Return Value
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Freg 8L-11R = Temporary Registers
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Freg 12L-21R = Preserved Registers
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Freg 22L-31R = Temporary Registers
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*/
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#define FIXED_REGISTERS \
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{0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 1, 0, 0, 1, 0, \
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/* fp registers */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0}
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/* 1 for registers not available across function calls.
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These must include the FIXED_REGISTERS and also any
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registers that can be used without being saved.
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The latter must include the registers where values are returned
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and the register where structure-value addresses are passed.
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Aside from that, you can include as many other registers as you like. */
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#define CALL_USED_REGISTERS \
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{1, 1, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* fp registers */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, \
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1}
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#define CONDITIONAL_REGISTER_USAGE \
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{ \
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int i; \
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if (!TARGET_PA_11) \
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{ \
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for (i = 56; i < 88; i++) \
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fixed_regs[i] = call_used_regs[i] = 1; \
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for (i = 33; i < 88; i += 2) \
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fixed_regs[i] = call_used_regs[i] = 1; \
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} \
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if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
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{ \
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for (i = 32; i < 88; i++) \
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fixed_regs[i] = call_used_regs[i] = 1; \
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} \
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if (flag_pic) \
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fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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}
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/* Allocate the call used registers first. This should minimize
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the number of registers that need to be saved (as call used
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registers will generally not be allocated across a call).
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Experimentation has shown slightly better results by allocating
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FP registers first. We allocate the caller-saved registers more
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or less in reverse order to their allocation as arguments.
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FP registers are ordered so that all L registers are selected before
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R registers. This works around a false dependency interlock on the
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PA8000 when accessing the high and low parts of an FP register
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independently. */
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#define REG_ALLOC_ORDER \
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{ \
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/* caller-saved fp regs. */ \
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68, 70, 72, 74, 76, 78, 80, 82, \
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84, 86, 40, 42, 44, 46, 38, 36, \
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34, 32, \
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69, 71, 73, 75, 77, 79, 81, 83, \
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85, 87, 41, 43, 45, 47, 39, 37, \
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35, 33, \
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/* caller-saved general regs. */ \
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28, 19, 20, 21, 22, 31, 27, 29, \
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23, 24, 25, 26, 2, \
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/* callee-saved fp regs. */ \
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48, 50, 52, 54, 56, 58, 60, 62, \
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64, 66, \
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49, 51, 53, 55, 57, 59, 61, 63, \
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65, 67, \
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/* callee-saved general regs. */ \
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3, 4, 5, 6, 7, 8, 9, 10, \
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11, 12, 13, 14, 15, 16, 17, 18, \
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/* special registers. */ \
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1, 30, 0, 88}
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/* Return number of consecutive hard regs needed starting at reg REGNO
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to hold something of mode MODE.
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This is ordinarily the length in words of a value of mode MODE
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but can be less for certain modes in special long registers.
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On the HP-PA, general registers are 32 bits wide. The floating
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point registers are 64 bits wide. Snake fp regs are treated as
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32 bits wide since the left and right parts are independently
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accessible. */
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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(FP_REGNO_P (REGNO) \
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? (!TARGET_PA_11 \
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? COMPLEX_MODE_P (MODE) ? 2 : 1 \
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: (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
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: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* There are no instructions that use DImode in PA 1.0, so we only
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allow it in PA 1.1 and later. */
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#define VALID_FP_MODE_P(MODE) \
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((MODE) == SFmode || (MODE) == DFmode \
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|| (MODE) == SCmode || (MODE) == DCmode \
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|| (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode))
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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On the HP-PA, the cpu registers can hold any mode that fits in 32 bits.
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For the 64-bit modes, we choose a set of non-overlapping general registers
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that includes the incoming arguments and the return value. We specify a
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set with no overlaps so that we don't have to specify that the destination
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register is an early clobber in patterns using this mode. Except for the
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return value, the starting registers are odd. For 128 and 256 bit modes,
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we similarly specify non-overlapping sets of cpu registers. However,
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there aren't any patterns defined for modes larger than 64 bits at the
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moment.
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We limit the modes allowed in the floating point registers to the
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set of modes used in the machine definition. In addition, we allow
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the complex modes SCmode and DCmode. The real and imaginary parts
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of complex modes are allocated to separate registers. This might
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allow patterns to be defined in the future to operate on these values.
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The PA 2.0 architecture specifies that quad-precision floating-point
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values should start on an even floating point register. Thus, we
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choose non-overlapping sets of registers starting on even register
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boundaries for large modes. However, there is currently no support
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in the machine definition for modes larger than 64 bits. TFmode is
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supported under HP-UX using libcalls. Since TFmode values are passed
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by reference, they never need to be loaded into the floating-point
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registers. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
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: !TARGET_PA_11 && FP_REGNO_P (REGNO) \
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? (VALID_FP_MODE_P (MODE) \
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&& (GET_MODE_SIZE (MODE) <= 8 \
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|| (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0))) \
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: FP_REGNO_P (REGNO) \
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? (VALID_FP_MODE_P (MODE) \
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&& (GET_MODE_SIZE (MODE) <= 4 \
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|| (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0) \
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|| (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0) \
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|| (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0))) \
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: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
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|| (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \
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&& ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \
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|| (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \
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&& ((REGNO) & 3) == 3 && (REGNO) <= 23) \
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|| (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD \
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&& ((REGNO) & 7) == 3 && (REGNO) <= 19)))
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/* How to renumber registers for dbx and gdb.
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Registers 0 - 31 remain unchanged.
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Registers 32 - 87 are mapped to 72 - 127
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Register 88 is mapped to 32. */
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#define DBX_REGISTER_NUMBER(REGNO) \
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((REGNO) <= 31 ? (REGNO) : \
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((REGNO) <= 87 ? (REGNO) + 40 : 32))
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/* We must not use the DBX register numbers for the DWARF 2 CFA column
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numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
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Instead use the identity mapping. */
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#define DWARF_FRAME_REGNUM(REG) REG
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/* Define the classes of registers for register constraints in the
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machine description. Also define ranges of constants.
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One of the classes must always be named ALL_REGS and include all hard regs.
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If there is more than one class, another class must be named NO_REGS
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and contain no registers.
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The name GENERAL_REGS must be the name of a class (or an alias for
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another name such as ALL_REGS). This is the class of registers
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that is allowed by "g" or "r" in a register constraint.
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Also, registers outside this class are allocated only when
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instructions express preferences for them.
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The classes must be numbered in nondecreasing order; that is,
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a larger-numbered class must never be contained completely
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in a smaller-numbered class.
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For any two classes, it is very desirable that there be another
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class that represents their union. */
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/* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
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1.1 fp regs, and the high 1.1 fp regs, to which the operands of
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fmpyadd and fmpysub are restricted. */
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enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
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GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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/* Give names of register classes as strings for dump file. */
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#define REG_CLASS_NAMES \
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{"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
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"GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
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/* Define which registers fit in which classes.
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This is an initializer for a vector of HARD_REG_SET
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of length N_REG_CLASSES. Register 0, the "condition code" register,
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is in no class. */
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#define REG_CLASS_CONTENTS \
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{{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \
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{0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \
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{0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \
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{0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \
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{0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \
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{0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \
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{0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \
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{0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */
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/* The following macro defines cover classes for Integrated Register
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Allocator. Cover classes is a set of non-intersected register
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classes covering all hard registers used for register allocation
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purpose. Any move between two registers of a cover class should be
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cheaper than load or store of the registers. The macro value is
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array of register classes with LIM_REG_CLASSES used as the end
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marker. */
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#define IRA_COVER_CLASSES \
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{ \
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GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \
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}
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/* Defines invalid mode changes. */
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#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
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pa_cannot_change_mode_class (FROM, TO, CLASS)
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/* Return the class number of the smallest class containing
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reg number REGNO. This could be a conditional expression
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or could index an array. */
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#define REGNO_REG_CLASS(REGNO) \
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((REGNO) == 0 ? NO_REGS \
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: (REGNO) == 1 ? R1_REGS \
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: (REGNO) < 32 ? GENERAL_REGS \
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: (REGNO) < 56 ? FP_REGS \
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: (REGNO) < 88 ? FPUPPER_REGS \
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: SHIFT_REGS)
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/* Return the maximum number of consecutive registers
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needed to represent mode MODE in a register of class CLASS. */
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \
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? (!TARGET_PA_11 \
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? COMPLEX_MODE_P (MODE) ? 2 : 1 \
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: (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
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: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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/* 1 if N is a possible register number for function argument passing. */
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#define FUNCTION_ARG_REGNO_P(N) \
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(((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
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/* How to refer to registers in assembler output.
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This sequence is indexed by compiler's hard-register-number (see above). */
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#define REGISTER_NAMES \
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{"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
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"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
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"%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
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"%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
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"%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \
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"%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R", \
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"%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \
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"%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \
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"%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \
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"%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \
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"%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \
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"SAR"}
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#define ADDITIONAL_REGISTER_NAMES \
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{{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \
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{"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \
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{"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \
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{"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \
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{"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \
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{"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \
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{"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \
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{"%cr11",88}}
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#define FP_SAVED_REG_LAST 66
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#define FP_SAVED_REG_FIRST 48
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#define FP_REG_STEP 2
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#define FP_REG_FIRST 32
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#define FP_REG_LAST 87
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