602 lines
15 KiB
C
602 lines
15 KiB
C
/* Xstormy16 cpu description.
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Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007,
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2008, 2009, 2010 Free Software Foundation, Inc.
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Contributed by Red Hat, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* Driver configuration. */
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#undef ASM_SPEC
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#define ASM_SPEC ""
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/* For xstormy16:
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- If -msim is specified, everything is built and linked as for the sim.
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- If -T is specified, that linker script is used, and it should provide
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appropriate libraries.
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- If neither is specified, everything is built as for the sim, but no
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I/O support is assumed. */
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#undef LIB_SPEC
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#define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)"
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#undef STARTFILE_SPEC
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#define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
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#undef ENDFILE_SPEC
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#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
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/* Run-time target specifications. */
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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builtin_define_std ("xstormy16"); \
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builtin_assert ("machine=xstormy16"); \
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builtin_assert ("cpu=xstormy16"); \
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} \
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while (0)
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#define TARGET_VERSION fprintf (stderr, " (xstormy16 cpu core)");
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#define CAN_DEBUG_WITHOUT_FP
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/* Storage Layout. */
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#define BITS_BIG_ENDIAN 1
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#define BYTES_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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#define UNITS_PER_WORD 2
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#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
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do \
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{ \
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if (GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) < 2) \
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(MODE) = HImode; \
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} \
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while (0)
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#define PARM_BOUNDARY 16
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#define STACK_BOUNDARY 16
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#define FUNCTION_BOUNDARY 16
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#define BIGGEST_ALIGNMENT 16
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#define DATA_ALIGNMENT(TYPE, ALIGN) \
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(TREE_CODE (TYPE) == ARRAY_TYPE \
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&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
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&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
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#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
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(TREE_CODE (EXP) == STRING_CST \
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&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
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#define STRICT_ALIGNMENT 1
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#define PCC_BITFIELD_TYPE_MATTERS 1
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/* Layout of Source Language Data Types. */
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#define INT_TYPE_SIZE 16
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#define SHORT_TYPE_SIZE 16
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#define LONG_TYPE_SIZE 32
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#define LONG_LONG_TYPE_SIZE 64
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#define FLOAT_TYPE_SIZE 32
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#define DOUBLE_TYPE_SIZE 64
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#define LONG_DOUBLE_TYPE_SIZE 64
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#define DEFAULT_SIGNED_CHAR 0
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#define SIZE_TYPE "unsigned int"
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#define PTRDIFF_TYPE "int"
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#undef WCHAR_TYPE_SIZE
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#define WCHAR_TYPE_SIZE 32
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/* Register Basics. */
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#define FIRST_PSEUDO_REGISTER 19
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#define FIXED_REGISTERS \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 }
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#define CALL_USED_REGISTERS \
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{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 }
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/* Order of allocation of registers. */
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#define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 }
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/* How Values Fit in Registers. */
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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#define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode)
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/* A C expression that is nonzero if it is desirable to choose register
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allocation so as to avoid move instructions between a value of mode MODE1
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and a value of mode MODE2.
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If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
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ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
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zero. */
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#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode)
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/* Register Classes. */
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enum reg_class
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{
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NO_REGS,
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R0_REGS,
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R1_REGS,
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TWO_REGS,
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R2_REGS,
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EIGHT_REGS,
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R8_REGS,
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ICALL_REGS,
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GENERAL_REGS,
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ALL_REGS,
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LIM_REG_CLASSES
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};
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#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
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#define IRA_COVER_CLASSES \
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{ \
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GENERAL_REGS, LIM_REG_CLASSES \
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}
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#define REG_CLASS_NAMES \
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{ \
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"NO_REGS", \
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"R0_REGS", \
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"R1_REGS", \
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"TWO_REGS", \
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"R2_REGS", \
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"EIGHT_REGS", \
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"R8_REGS", \
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"ICALL_REGS", \
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"GENERAL_REGS", \
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"ALL_REGS" \
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}
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#define REG_CLASS_CONTENTS \
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{ \
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{ 0x00000 }, \
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{ 0x00001 }, \
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{ 0x00002 }, \
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{ 0x00003 }, \
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{ 0x00004 }, \
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{ 0x000FF }, \
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{ 0x00100 }, \
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{ 0x00300 }, \
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{ 0x6FFFF }, \
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{ (1 << FIRST_PSEUDO_REGISTER) - 1 } \
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}
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#define REGNO_REG_CLASS(REGNO) \
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( (REGNO) == 0 ? R0_REGS \
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: (REGNO) == 1 ? R1_REGS \
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: (REGNO) == 2 ? R2_REGS \
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: (REGNO) < 8 ? EIGHT_REGS \
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: (REGNO) == 8 ? R8_REGS \
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: (REGNO) <= 18 ? GENERAL_REGS \
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: ALL_REGS)
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#define BASE_REG_CLASS GENERAL_REGS
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#define INDEX_REG_CLASS GENERAL_REGS
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/* The following letters are unavailable, due to being used as
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constraints:
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'0'..'9'
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'<', '>'
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'E', 'F', 'G', 'H'
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'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
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'Q', 'R', 'S', 'T', 'U'
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'V', 'X'
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'g', 'i', 'm', 'n', 'o', 'p', 'r', 's'. */
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#define REG_CLASS_FROM_LETTER(CHAR) \
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( (CHAR) == 'a' ? R0_REGS \
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: (CHAR) == 'b' ? R1_REGS \
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: (CHAR) == 'c' ? R2_REGS \
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: (CHAR) == 'd' ? R8_REGS \
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: (CHAR) == 'e' ? EIGHT_REGS \
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: (CHAR) == 't' ? TWO_REGS \
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: (CHAR) == 'z' ? ICALL_REGS \
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: NO_REGS)
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#define REGNO_OK_FOR_BASE_P(NUM) 1
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#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
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#define PREFERRED_RELOAD_CLASS(X, CLASS) \
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xstormy16_preferred_reload_class (X, CLASS)
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#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
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xstormy16_preferred_reload_class (X, CLASS)
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/* This chip has the interesting property that only the first eight
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registers can be moved to/from memory. */
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#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
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xstormy16_secondary_reload_class (CLASS, MODE, X)
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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#define CONST_OK_FOR_LETTER_P(VALUE, C) \
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( (C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 3 \
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: (C) == 'J' ? exact_log2 (VALUE) != -1 \
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: (C) == 'K' ? exact_log2 (~(VALUE)) != -1 \
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: (C) == 'L' ? (VALUE) >= 0 && (VALUE) <= 255 \
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: (C) == 'M' ? (VALUE) >= -255 && (VALUE) <= 0 \
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: (C) == 'N' ? (VALUE) >= -3 && (VALUE) <= 0 \
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: (C) == 'O' ? (VALUE) >= 1 && (VALUE) <= 4 \
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: (C) == 'P' ? (VALUE) >= -4 && (VALUE) <= -1 \
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: 0 )
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#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
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#define EXTRA_CONSTRAINT(VALUE, C) \
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xstormy16_extra_constraint_p (VALUE, C)
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/* Basic Stack Layout. */
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/* We want to use post-increment instructions to push things on the stack,
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because we don't have any pre-increment ones. */
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#define STACK_PUSH_CODE POST_INC
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#define FRAME_GROWS_DOWNWARD 0
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#define ARGS_GROW_DOWNWARD 1
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#define STARTING_FRAME_OFFSET 0
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#define FIRST_PARM_OFFSET(FUNDECL) 0
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#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
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((COUNT) == 0 \
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? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
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: NULL_RTX)
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#define INCOMING_RETURN_ADDR_RTX \
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gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4)))
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#define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4)
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/* Register That Address the Stack Frame. */
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#define STATIC_CHAIN_REGNUM 1
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#define HARD_FRAME_POINTER_REGNUM 13
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#define STACK_POINTER_REGNUM 15
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#define CARRY_REGNUM 16
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#define FRAME_POINTER_REGNUM 17
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#define ARG_POINTER_REGNUM 18
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/* Eliminating the Frame Pointer and the Arg Pointer. */
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#define ELIMINABLE_REGS \
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{ \
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{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
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{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
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}
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#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
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(OFFSET) = xstormy16_initial_elimination_offset (FROM, TO)
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/* Passing Function Arguments on the Stack. */
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#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
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#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
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/* Function Arguments in Registers. */
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#define NUM_ARGUMENT_REGISTERS 6
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#define FIRST_ARGUMENT_REGISTER 2
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#define XSTORMY16_WORD_SIZE(TYPE, MODE) \
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((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
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+ 1) \
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/ 2)
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#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
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xstormy16_function_arg (CUM, MODE, TYPE, NAMED)
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/* For this platform, the value of CUMULATIVE_ARGS is the number of words
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of arguments that have been passed in registers so far. */
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#define CUMULATIVE_ARGS int
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#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
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(CUM) = 0
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#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
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((CUM) = xstormy16_function_arg_advance (CUM, MODE, TYPE, NAMED))
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#define FUNCTION_ARG_REGNO_P(REGNO) \
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((REGNO) >= FIRST_ARGUMENT_REGISTER \
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&& (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS)
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/* How Scalar Function Values are Returned. */
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/* The number of the hard register that is used to return a scalar value from a
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function call. */
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#define RETURN_VALUE_REGNUM FIRST_ARGUMENT_REGISTER
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#define FUNCTION_VALUE(VALTYPE, FUNC) \
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xstormy16_function_value (VALTYPE, FUNC)
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#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RETURN_VALUE_REGNUM)
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#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == RETURN_VALUE_REGNUM)
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/* Function Entry and Exit. */
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#define EPILOGUE_USES(REGNO) \
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xstormy16_epilogue_uses (REGNO)
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/* Generating Code for Profiling. */
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/* This declaration must be present, but it can be an abort if profiling is
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not implemented. */
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#define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler ()
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/* Trampolines for Nested Functions. */
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#define TRAMPOLINE_SIZE 8
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#define TRAMPOLINE_ALIGNMENT 16
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/* Addressing Modes. */
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#define HAVE_POST_INCREMENT 1
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#define HAVE_PRE_DECREMENT 1
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#define MAX_REGS_PER_ADDRESS 1
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#ifdef REG_OK_STRICT
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#define REG_OK_FOR_BASE_P(X) \
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(REGNO_OK_FOR_BASE_P (REGNO (X)) && (REGNO (X) < FIRST_PSEUDO_REGISTER))
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#else
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#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
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#endif
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#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
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/* On this chip, this is true if the address is valid with an offset
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of 0 but not of 6, because in that case it cannot be used as an
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address for DImode or DFmode, or if the address is a post-increment
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or pre-decrement address. */
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#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
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if (xstormy16_mode_dependent_address_p (ADDR)) \
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goto LABEL
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#define LEGITIMATE_CONSTANT_P(X) 1
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/* Describing Relative Costs of Operations. */
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#define REGISTER_MOVE_COST(MODE, FROM, TO) 2
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#define MEMORY_MOVE_COST(M,C,I) (5 + memory_move_secondary_cost (M, C, I))
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#define BRANCH_COST(speed_p, predictable_p) 5
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#define SLOW_BYTE_ACCESS 0
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#define NO_FUNCTION_CSE
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/* Dividing the output into sections. */
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#define TEXT_SECTION_ASM_OP ".text"
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#define DATA_SECTION_ASM_OP ".data"
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#define BSS_SECTION_ASM_OP "\t.section\t.bss"
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/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
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There are no shared libraries on this target so these sections need
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not be writable.
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Defined in elfos.h. */
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#undef CTORS_SECTION_ASM_OP
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#undef DTORS_SECTION_ASM_OP
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#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
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#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
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#define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections
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#define JUMP_TABLES_IN_TEXT_SECTION 1
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/* The Overall Framework of an Assembler File. */
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#define ASM_COMMENT_START ";"
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#define ASM_APP_ON "#APP\n"
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#define ASM_APP_OFF "#NO_APP\n"
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/* Output of Data. */
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#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|')
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#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
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xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
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#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
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xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
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/* Output and Generation of Labels. */
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#define SYMBOL_FLAG_XSTORMY16_BELOW100 (SYMBOL_FLAG_MACH_DEP << 0)
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#define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \
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do \
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{ \
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const char *rn = XSTR (SYMBOL, 0); \
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\
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if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \
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ASM_OUTPUT_LABEL_REF ((STREAM), rn); \
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else \
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assemble_name (STREAM, rn); \
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} \
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while (0)
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#define ASM_OUTPUT_LABEL_REF(STREAM, NAME) \
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do \
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{ \
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fputs ("@fptr(", STREAM); \
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assemble_name (STREAM, NAME); \
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fputc (')', STREAM); \
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} \
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while (0)
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/* Globalizing directive for a label. */
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#define GLOBAL_ASM_OP "\t.globl "
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/* Output of Assembler Instructions. */
|
||
|
||
#define REGISTER_NAMES \
|
||
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
|
||
"r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" }
|
||
|
||
#define ADDITIONAL_REGISTER_NAMES \
|
||
{ { "r14", 14 }, \
|
||
{ "r15", 15 } }
|
||
|
||
#define PRINT_OPERAND(STREAM, X, CODE) xstormy16_print_operand (STREAM, X, CODE)
|
||
|
||
#define PRINT_OPERAND_ADDRESS(STREAM, X) xstormy16_print_operand_address (STREAM, X)
|
||
|
||
/* USER_LABEL_PREFIX is defined in svr4.h. */
|
||
#define REGISTER_PREFIX ""
|
||
#define LOCAL_LABEL_PREFIX "."
|
||
#define USER_LABEL_PREFIX ""
|
||
#define IMMEDIATE_PREFIX "#"
|
||
|
||
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
|
||
fprintf (STREAM, "\tpush %d\n", REGNO)
|
||
|
||
#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
|
||
fprintf (STREAM, "\tpop %d\n", REGNO)
|
||
|
||
|
||
/* Output of dispatch tables. */
|
||
|
||
/* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because
|
||
this could cause label alignment to appear between the 'br' and the table,
|
||
which would be bad. Instead, it controls the output of the table
|
||
itself. */
|
||
#define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \
|
||
xstormy16_output_addr_vec (file, LABEL, BODY)
|
||
|
||
/* Alignment for ADDR_VECs is the same as for code. */
|
||
#define ADDR_VEC_ALIGN(ADDR_VEC) 1
|
||
|
||
|
||
/* Assembler Commands for Exception Regions. */
|
||
|
||
#define DWARF2_UNWIND_INFO 0
|
||
#define DWARF_CIE_DATA_ALIGNMENT 1
|
||
|
||
#undef DONT_USE_BUILTIN_SETJMP
|
||
#define JMP_BUF_SIZE 8
|
||
|
||
/* Assembler Commands for Alignment. */
|
||
|
||
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
|
||
fprintf ((STREAM), "\t.p2align %d\n", (POWER))
|
||
|
||
|
||
/* Macros Affecting all Debug Formats. */
|
||
|
||
/* Defined in svr4.h. */
|
||
#undef PREFERRED_DEBUGGING_TYPE
|
||
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
||
|
||
|
||
/* Macros for SDB and Dwarf Output. */
|
||
|
||
/* Define this macro if addresses in Dwarf 2 debugging info should not
|
||
be the same size as pointers on the target architecture. The
|
||
macro's value should be the size, in bytes, to use for addresses in
|
||
the debugging info.
|
||
|
||
Some architectures use word addresses to refer to code locations,
|
||
but Dwarf 2 info always uses byte addresses. On such machines,
|
||
Dwarf 2 addresses need to be larger than the architecture's
|
||
pointers. */
|
||
#define DWARF2_ADDR_SIZE 4
|
||
|
||
|
||
/* Miscellaneous Parameters. */
|
||
|
||
#define CASE_VECTOR_MODE SImode
|
||
|
||
#define WORD_REGISTER_OPERATIONS
|
||
|
||
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
|
||
|
||
#define MOVE_MAX 2
|
||
|
||
#define SHIFT_COUNT_TRUNCATED 1
|
||
|
||
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
||
|
||
#define Pmode HImode
|
||
|
||
#define FUNCTION_MODE HImode
|
||
|
||
#define NO_IMPLICIT_EXTERN_C
|
||
|
||
#define HANDLE_SYSV_PRAGMA 1
|