411 lines
14 KiB
Markdown
411 lines
14 KiB
Markdown
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;; Scheduling description for IBM Power4 and PowerPC 970 processors.
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;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Sources: IBM Red Book and White Paper on POWER4
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;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
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;; Instructions that update more than one register get broken into two
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;; (split) or more internal ops. The chip can issue up to 5
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;; internal ops per cycle.
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(define_automaton "power4iu,power4fpu,power4vec,power4misc")
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(define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
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(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
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(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
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(define_cpu_unit "bpu_power4,cru_power4" "power4misc")
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(define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
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(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
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"power4misc")
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(define_reservation "lsq_power4"
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"(du1_power4,lsu1_power4)\
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|(du2_power4,lsu2_power4)\
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|(du3_power4,lsu2_power4)\
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|(du4_power4,lsu1_power4)")
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(define_reservation "lsuq_power4"
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"((du1_power4+du2_power4,lsu1_power4)\
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|(du2_power4+du3_power4,lsu2_power4)\
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|(du3_power4+du4_power4,lsu2_power4))\
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+(nothing,iu2_power4|nothing,iu1_power4)")
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(define_reservation "iq_power4"
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"(du1_power4|du2_power4|du3_power4|du4_power4),\
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(iu1_power4|iu2_power4)")
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(define_reservation "fpq_power4"
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"(du1_power4|du2_power4|du3_power4|du4_power4),\
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(fpu1_power4|fpu2_power4)")
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(define_reservation "vq_power4"
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"(du1_power4,vec_power4)\
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|(du2_power4,vec_power4)\
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|(du3_power4,vec_power4)\
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|(du4_power4,vec_power4)")
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(define_reservation "vpq_power4"
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"(du1_power4,vecperm_power4)\
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|(du2_power4,vecperm_power4)\
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|(du3_power4,vecperm_power4)\
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|(du4_power4,vecperm_power4)")
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; Dispatch slots are allocated in order conforming to program order.
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(absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
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(absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
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(absence_set "du3_power4" "du4_power4,du5_power4")
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(absence_set "du4_power4" "du5_power4")
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; Load/store
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(define_insn_reservation "power4-load" 4 ; 3
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "power4"))
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"lsq_power4")
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(define_insn_reservation "power4-load-ext" 5
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(and (eq_attr "type" "load_ext")
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(eq_attr "cpu" "power4"))
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"(du1_power4+du2_power4,lsu1_power4\
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|du2_power4+du3_power4,lsu2_power4\
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|du3_power4+du4_power4,lsu2_power4),\
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nothing,nothing,\
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(iu2_power4|iu1_power4)")
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(define_insn_reservation "power4-load-ext-update" 5
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(and (eq_attr "type" "load_ext_u")
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(eq_attr "cpu" "power4"))
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"du1_power4+du2_power4+du3_power4+du4_power4,\
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lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
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(define_insn_reservation "power4-load-ext-update-indexed" 5
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(and (eq_attr "type" "load_ext_ux")
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(eq_attr "cpu" "power4"))
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"du1_power4+du2_power4+du3_power4+du4_power4,\
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iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
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(define_insn_reservation "power4-load-update-indexed" 3
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(and (eq_attr "type" "load_ux")
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(eq_attr "cpu" "power4"))
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"du1_power4+du2_power4+du3_power4+du4_power4,\
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iu1_power4,lsu2_power4+iu2_power4")
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(define_insn_reservation "power4-load-update" 4 ; 3
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(and (eq_attr "type" "load_u")
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(eq_attr "cpu" "power4"))
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"lsuq_power4")
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(define_insn_reservation "power4-fpload" 6 ; 5
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "power4"))
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"lsq_power4")
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(define_insn_reservation "power4-fpload-update" 6 ; 5
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(and (eq_attr "type" "fpload_u,fpload_ux")
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(eq_attr "cpu" "power4"))
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"lsuq_power4")
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(define_insn_reservation "power4-vecload" 6 ; 5
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(and (eq_attr "type" "vecload")
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(eq_attr "cpu" "power4"))
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"lsq_power4")
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(define_insn_reservation "power4-store" 12
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(and (eq_attr "type" "store")
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(eq_attr "cpu" "power4"))
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"((du1_power4,lsu1_power4)\
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|(du2_power4,lsu2_power4)\
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|(du3_power4,lsu2_power4)\
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|(du4_power4,lsu1_power4)),\
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(iu1_power4|iu2_power4)")
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(define_insn_reservation "power4-store-update" 12
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(and (eq_attr "type" "store_u")
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(eq_attr "cpu" "power4"))
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"((du1_power4+du2_power4,lsu1_power4)\
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|(du2_power4+du3_power4,lsu2_power4)\
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|(du3_power4+du4_power4,lsu2_power4)\
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|(du3_power4+du4_power4,lsu2_power4))+\
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((nothing,iu2_power4,iu1_power4)\
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|(nothing,iu2_power4,iu2_power4)\
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|(nothing,iu1_power4,iu2_power4)\
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|(nothing,iu1_power4,iu2_power4))")
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(define_insn_reservation "power4-store-update-indexed" 12
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(and (eq_attr "type" "store_ux")
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(eq_attr "cpu" "power4"))
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"du1_power4+du2_power4+du3_power4+du4_power4,\
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iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
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(define_insn_reservation "power4-fpstore" 12
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(and (eq_attr "type" "fpstore")
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(eq_attr "cpu" "power4"))
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"((du1_power4,lsu1_power4)\
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|(du2_power4,lsu2_power4)\
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|(du3_power4,lsu2_power4)\
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|(du4_power4,lsu1_power4)),\
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(fpu1_power4|fpu2_power4)")
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(define_insn_reservation "power4-fpstore-update" 12
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(and (eq_attr "type" "fpstore_u,fpstore_ux")
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(eq_attr "cpu" "power4"))
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"((du1_power4+du2_power4,lsu1_power4)\
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|(du2_power4+du3_power4,lsu2_power4)\
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|(du3_power4+du4_power4,lsu2_power4))\
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+(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))")
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(define_insn_reservation "power4-vecstore" 12
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(and (eq_attr "type" "vecstore")
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(eq_attr "cpu" "power4"))
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"(du1_power4,lsu1_power4,vec_power4)\
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|(du2_power4,lsu2_power4,vec_power4)\
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|(du3_power4,lsu2_power4,vec_power4)\
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|(du4_power4,lsu1_power4,vec_power4)")
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(define_insn_reservation "power4-llsc" 11
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(and (eq_attr "type" "load_l,store_c,sync")
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(eq_attr "cpu" "power4"))
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"du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
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; Integer latency is 2 cycles
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(define_insn_reservation "power4-integer" 2
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(and (eq_attr "type" "integer,insert_dword,shift,trap,\
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var_shift_rotate,cntlz,exts,isel")
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(eq_attr "cpu" "power4"))
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"iq_power4")
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(define_insn_reservation "power4-two" 2
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "power4"))
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"((du1_power4+du2_power4)\
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|(du2_power4+du3_power4)\
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|(du3_power4+du4_power4)\
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|(du4_power4+du1_power4)),\
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((iu1_power4,nothing,iu2_power4)\
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|(iu2_power4,nothing,iu2_power4)\
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|(iu2_power4,nothing,iu1_power4)\
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|(iu1_power4,nothing,iu1_power4))")
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(define_insn_reservation "power4-three" 2
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "power4"))
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"(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\
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|du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\
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((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
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|(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
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|(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
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|(iu1_power4,nothing,iu2_power4,nothing,iu2_power4))")
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(define_insn_reservation "power4-insert" 4
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(and (eq_attr "type" "insert_word")
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(eq_attr "cpu" "power4"))
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"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
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((iu1_power4,nothing,iu2_power4)\
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|(iu2_power4,nothing,iu2_power4)\
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|(iu2_power4,nothing,iu1_power4))")
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(define_insn_reservation "power4-cmp" 3
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(and (eq_attr "type" "cmp,fast_compare")
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(eq_attr "cpu" "power4"))
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"iq_power4")
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(define_insn_reservation "power4-compare" 2
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(and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
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(eq_attr "cpu" "power4"))
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"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
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((iu1_power4,iu2_power4)\
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|(iu2_power4,iu2_power4)\
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|(iu2_power4,iu1_power4))")
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(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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(define_insn_reservation "power4-lmul-cmp" 7
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(and (eq_attr "type" "lmul_compare")
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(eq_attr "cpu" "power4"))
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"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
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((iu1_power4*6,iu2_power4)\
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|(iu2_power4*6,iu2_power4)\
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|(iu2_power4*6,iu1_power4))")
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(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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(define_insn_reservation "power4-imul-cmp" 5
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(and (eq_attr "type" "imul_compare")
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(eq_attr "cpu" "power4"))
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"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
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((iu1_power4*4,iu2_power4)\
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|(iu2_power4*4,iu2_power4)\
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|(iu2_power4*4,iu1_power4))")
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(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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(define_insn_reservation "power4-lmul" 7
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(and (eq_attr "type" "lmul")
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(eq_attr "cpu" "power4"))
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"(du1_power4|du2_power4|du3_power4|du4_power4),\
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(iu1_power4*6|iu2_power4*6)")
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(define_insn_reservation "power4-imul" 5
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(and (eq_attr "type" "imul")
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(eq_attr "cpu" "power4"))
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"(du1_power4|du2_power4|du3_power4|du4_power4),\
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(iu1_power4*4|iu2_power4*4)")
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(define_insn_reservation "power4-imul3" 4
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(and (eq_attr "type" "imul2,imul3")
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(eq_attr "cpu" "power4"))
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"(du1_power4|du2_power4|du3_power4|du4_power4),\
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(iu1_power4*3|iu2_power4*3)")
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; SPR move only executes in first IU.
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; Integer division only executes in second IU.
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(define_insn_reservation "power4-idiv" 36
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "power4"))
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"du1_power4+du2_power4,iu2_power4*35")
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(define_insn_reservation "power4-ldiv" 68
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(and (eq_attr "type" "ldiv")
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(eq_attr "cpu" "power4"))
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"du1_power4+du2_power4,iu2_power4*67")
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(define_insn_reservation "power4-mtjmpr" 3
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(eq_attr "cpu" "power4"))
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"du1_power4,bpu_power4")
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; Branches take dispatch Slot 4. The presence_sets prevent other insn from
|
||
|
|
; grabbing previous dispatch slots once this is assigned.
|
||
|
|
(define_insn_reservation "power4-branch" 2
|
||
|
|
(and (eq_attr "type" "jmpreg,branch")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"(du5_power4\
|
||
|
|
|du4_power4+du5_power4\
|
||
|
|
|du3_power4+du4_power4+du5_power4\
|
||
|
|
|du2_power4+du3_power4+du4_power4+du5_power4\
|
||
|
|
|du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
|
||
|
|
|
||
|
|
|
||
|
|
; Condition Register logical ops are split if non-destructive (RT != RB)
|
||
|
|
(define_insn_reservation "power4-crlogical" 2
|
||
|
|
(and (eq_attr "type" "cr_logical")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"du1_power4,cru_power4")
|
||
|
|
|
||
|
|
(define_insn_reservation "power4-delayedcr" 4
|
||
|
|
(and (eq_attr "type" "delayed_cr")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"du1_power4+du2_power4,cru_power4,cru_power4")
|
||
|
|
|
||
|
|
; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
|
||
|
|
(define_insn_reservation "power4-mfcr" 6
|
||
|
|
(and (eq_attr "type" "mfcr")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"du1_power4+du2_power4+du3_power4+du4_power4,\
|
||
|
|
du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
|
||
|
|
cru_power4,cru_power4,cru_power4")
|
||
|
|
|
||
|
|
; mfcrf (1 field)
|
||
|
|
(define_insn_reservation "power4-mfcrf" 3
|
||
|
|
(and (eq_attr "type" "mfcrf")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"du1_power4,cru_power4")
|
||
|
|
|
||
|
|
; mtcrf (1 field)
|
||
|
|
(define_insn_reservation "power4-mtcr" 4
|
||
|
|
(and (eq_attr "type" "mtcr")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"du1_power4,iu1_power4")
|
||
|
|
|
||
|
|
; Basic FP latency is 6 cycles
|
||
|
|
(define_insn_reservation "power4-fp" 6
|
||
|
|
(and (eq_attr "type" "fp,dmul")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"fpq_power4")
|
||
|
|
|
||
|
|
(define_insn_reservation "power4-fpcompare" 5
|
||
|
|
(and (eq_attr "type" "fpcompare")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"fpq_power4")
|
||
|
|
|
||
|
|
(define_insn_reservation "power4-sdiv" 33
|
||
|
|
(and (eq_attr "type" "sdiv,ddiv")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"(du1_power4|du2_power4|du3_power4|du4_power4),\
|
||
|
|
(fpu1_power4*28|fpu2_power4*28)")
|
||
|
|
|
||
|
|
(define_insn_reservation "power4-sqrt" 40
|
||
|
|
(and (eq_attr "type" "ssqrt,dsqrt")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"(du1_power4|du2_power4|du3_power4|du4_power4),\
|
||
|
|
(fpu1_power4*35|fpu2_power4*35)")
|
||
|
|
|
||
|
|
(define_insn_reservation "power4-isync" 2
|
||
|
|
(and (eq_attr "type" "isync")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
|
||
|
|
|
||
|
|
|
||
|
|
; VMX
|
||
|
|
(define_insn_reservation "power4-vecsimple" 2
|
||
|
|
(and (eq_attr "type" "vecsimple")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"vq_power4")
|
||
|
|
|
||
|
|
(define_insn_reservation "power4-veccomplex" 5
|
||
|
|
(and (eq_attr "type" "veccomplex")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"vq_power4")
|
||
|
|
|
||
|
|
; vecfp compare
|
||
|
|
(define_insn_reservation "power4-veccmp" 8
|
||
|
|
(and (eq_attr "type" "veccmp")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"vq_power4")
|
||
|
|
|
||
|
|
(define_insn_reservation "power4-vecfloat" 8
|
||
|
|
(and (eq_attr "type" "vecfloat")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"vq_power4")
|
||
|
|
|
||
|
|
(define_insn_reservation "power4-vecperm" 2
|
||
|
|
(and (eq_attr "type" "vecperm")
|
||
|
|
(eq_attr "cpu" "power4"))
|
||
|
|
"vpq_power4")
|
||
|
|
|
||
|
|
(define_bypass 4 "power4-vecload" "power4-vecperm")
|
||
|
|
|
||
|
|
(define_bypass 3 "power4-vecsimple" "power4-vecperm")
|
||
|
|
(define_bypass 6 "power4-veccomplex" "power4-vecperm")
|
||
|
|
(define_bypass 3 "power4-vecperm"
|
||
|
|
"power4-vecsimple,power4-veccomplex,power4-vecfloat")
|
||
|
|
(define_bypass 9 "power4-vecfloat" "power4-vecperm")
|
||
|
|
|
||
|
|
(define_bypass 5 "power4-vecsimple,power4-veccomplex"
|
||
|
|
"power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
|
||
|
|
|
||
|
|
(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
|
||
|
|
(define_bypass 7 "power4-veccomplex" "power4-vecstore")
|
||
|
|
(define_bypass 10 "power4-vecfloat" "power4-vecstore")
|