608 lines
20 KiB
Markdown
608 lines
20 KiB
Markdown
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;; Copyright (C) 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;
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; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
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(define_insn "mips_absq_s_qb"
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[(parallel
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[(set (match_operand:V4QI 0 "register_operand" "=d")
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(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
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UNSPEC_ABSQ_S_QB))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
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"ISA_HAS_DSPR2"
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"absq_s.qb\t%0,%z1"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_addu_ph"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
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"ISA_HAS_DSPR2"
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"addu.ph\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_addu_s_ph"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_ADDU_S_PH))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
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"ISA_HAS_DSPR2"
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"addu_s.ph\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_adduh_qb"
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[(set (match_operand:V4QI 0 "register_operand" "=d")
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(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_ADDUH_QB))]
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"ISA_HAS_DSPR2"
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"adduh.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_adduh_r_qb"
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[(set (match_operand:V4QI 0 "register_operand" "=d")
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(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_ADDUH_R_QB))]
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"ISA_HAS_DSPR2"
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"adduh_r.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_append"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "reg_or_0_operand" "dJ")
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(match_operand:SI 3 "const_int_operand" "n")]
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UNSPEC_APPEND))]
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"ISA_HAS_DSPR2"
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{
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if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
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operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
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return "append\t%0,%z2,%3";
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}
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_balign"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "reg_or_0_operand" "dJ")
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(match_operand:SI 3 "const_int_operand" "n")]
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UNSPEC_BALIGN))]
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"ISA_HAS_DSPR2"
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{
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if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
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operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
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return "balign\t%0,%z2,%3";
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}
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_cmpgdu_eq_qb"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_CMPGDU_EQ_QB))
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(set (reg:CCDSP CCDSP_CC_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)
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(reg:CCDSP CCDSP_CC_REGNUM)]
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UNSPEC_CMPGDU_EQ_QB))])]
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"ISA_HAS_DSPR2"
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"cmpgdu.eq.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_cmpgdu_lt_qb"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_CMPGDU_LT_QB))
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(set (reg:CCDSP CCDSP_CC_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)
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(reg:CCDSP CCDSP_CC_REGNUM)]
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UNSPEC_CMPGDU_LT_QB))])]
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"ISA_HAS_DSPR2"
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"cmpgdu.lt.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_cmpgdu_le_qb"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_CMPGDU_LE_QB))
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(set (reg:CCDSP CCDSP_CC_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)
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(reg:CCDSP CCDSP_CC_REGNUM)]
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UNSPEC_CMPGDU_LE_QB))])]
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"ISA_HAS_DSPR2"
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"cmpgdu.le.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_dpa_w_ph"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(unspec:DI [(match_operand:DI 1 "register_operand" "0")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
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UNSPEC_DPA_W_PH))]
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"ISA_HAS_DSPR2 && !TARGET_64BIT"
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"dpa.w.ph\t%q0,%z2,%z3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_dps_w_ph"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(unspec:DI [(match_operand:DI 1 "register_operand" "0")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
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UNSPEC_DPS_W_PH))]
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"ISA_HAS_DSPR2 && !TARGET_64BIT"
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"dps.w.ph\t%q0,%z2,%z3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_expand "mips_madd<u>"
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[(set (match_operand:DI 0 "register_operand")
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(plus:DI
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(mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
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(any_extend:DI (match_operand:SI 3 "register_operand")))
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(match_operand:DI 1 "register_operand")))]
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"ISA_HAS_DSPR2 && !TARGET_64BIT")
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(define_expand "mips_msub<u>"
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[(set (match_operand:DI 0 "register_operand")
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(minus:DI
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(match_operand:DI 1 "register_operand")
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(mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
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(any_extend:DI (match_operand:SI 3 "register_operand")))))]
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"ISA_HAS_DSPR2 && !TARGET_64BIT")
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(define_insn "mulv2hi3"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
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(match_operand:V2HI 2 "register_operand" "d")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
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(clobber (match_scratch:DI 3 "=x"))])]
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"ISA_HAS_DSPR2"
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"mul.ph\t%0,%1,%2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mul_s_ph"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_MUL_S_PH))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
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(clobber (match_scratch:DI 3 "=x"))])]
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"ISA_HAS_DSPR2"
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"mul_s.ph\t%0,%z1,%z2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mulq_rs_w"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
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(match_operand:SI 2 "reg_or_0_operand" "dJ")]
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UNSPEC_MULQ_RS_W))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
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(clobber (match_scratch:DI 3 "=x"))])]
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"ISA_HAS_DSPR2"
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"mulq_rs.w\t%0,%z1,%z2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mulq_s_ph"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_MULQ_S_PH))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
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(clobber (match_scratch:DI 3 "=x"))])]
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"ISA_HAS_DSPR2"
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"mulq_s.ph\t%0,%z1,%z2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mulq_s_w"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
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(match_operand:SI 2 "reg_or_0_operand" "dJ")]
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UNSPEC_MULQ_S_W))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
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(clobber (match_scratch:DI 3 "=x"))])]
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"ISA_HAS_DSPR2"
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"mulq_s.w\t%0,%z1,%z2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mulsa_w_ph"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(unspec:DI [(match_operand:DI 1 "register_operand" "0")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
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UNSPEC_MULSA_W_PH))]
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"ISA_HAS_DSPR2 && !TARGET_64BIT"
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"mulsa.w.ph\t%q0,%z2,%z3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_mult"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
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(sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
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"ISA_HAS_DSPR2 && !TARGET_64BIT"
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"mult\t%q0,%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")])
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(define_insn "mips_multu"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
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(zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
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"ISA_HAS_DSPR2 && !TARGET_64BIT"
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"multu\t%q0,%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_precr_qb_ph"
|
||
|
|
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
||
|
|
(unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_PRECR_QB_PH))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"precr.qb.ph\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_precr_sra_ph_w"
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||
|
|
(unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
|
||
|
|
(match_operand:SI 2 "reg_or_0_operand" "dJ")
|
||
|
|
(match_operand:SI 3 "const_int_operand" "n")]
|
||
|
|
UNSPEC_PRECR_SRA_PH_W))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
{
|
||
|
|
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
|
||
|
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
|
||
|
|
return "precr_sra.ph.w\t%0,%z2,%3";
|
||
|
|
}
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_precr_sra_r_ph_w"
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||
|
|
(unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
|
||
|
|
(match_operand:SI 2 "reg_or_0_operand" "dJ")
|
||
|
|
(match_operand:SI 3 "const_int_operand" "n")]
|
||
|
|
UNSPEC_PRECR_SRA_R_PH_W))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
{
|
||
|
|
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
|
||
|
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
|
||
|
|
return "precr_sra_r.ph.w\t%0,%z2,%3";
|
||
|
|
}
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_prepend"
|
||
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
||
|
|
(unspec:SI [(match_operand:SI 1 "register_operand" "0")
|
||
|
|
(match_operand:SI 2 "reg_or_0_operand" "dJ")
|
||
|
|
(match_operand:SI 3 "const_int_operand" "n")]
|
||
|
|
UNSPEC_PREPEND))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
{
|
||
|
|
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
|
||
|
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
|
||
|
|
return "prepend\t%0,%z2,%3";
|
||
|
|
}
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_shra_qb"
|
||
|
|
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
|
||
|
|
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
|
||
|
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
||
|
|
UNSPEC_SHRA_QB))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
{
|
||
|
|
if (which_alternative == 0)
|
||
|
|
{
|
||
|
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
|
||
|
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
|
||
|
|
return "shra.qb\t%0,%z1,%2";
|
||
|
|
}
|
||
|
|
return "shrav.qb\t%0,%z1,%2";
|
||
|
|
}
|
||
|
|
[(set_attr "type" "shift")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
|
||
|
|
(define_insn "mips_shra_r_qb"
|
||
|
|
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
|
||
|
|
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
|
||
|
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
||
|
|
UNSPEC_SHRA_R_QB))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
{
|
||
|
|
if (which_alternative == 0)
|
||
|
|
{
|
||
|
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
|
||
|
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
|
||
|
|
return "shra_r.qb\t%0,%z1,%2";
|
||
|
|
}
|
||
|
|
return "shrav_r.qb\t%0,%z1,%2";
|
||
|
|
}
|
||
|
|
[(set_attr "type" "shift")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_shrl_ph"
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d,d")
|
||
|
|
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
|
||
|
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
||
|
|
UNSPEC_SHRL_PH))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
{
|
||
|
|
if (which_alternative == 0)
|
||
|
|
{
|
||
|
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
|
||
|
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
|
||
|
|
return "shrl.ph\t%0,%z1,%2";
|
||
|
|
}
|
||
|
|
return "shrlv.ph\t%0,%z1,%2";
|
||
|
|
}
|
||
|
|
[(set_attr "type" "shift")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_subu_ph"
|
||
|
|
[(parallel
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||
|
|
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_SUBU_PH))
|
||
|
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||
|
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"subu.ph\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_subu_s_ph"
|
||
|
|
[(parallel
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||
|
|
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_SUBU_S_PH))
|
||
|
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||
|
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"subu_s.ph\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_subuh_qb"
|
||
|
|
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
||
|
|
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_SUBUH_QB))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"subuh.qb\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_subuh_r_qb"
|
||
|
|
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
||
|
|
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_SUBUH_R_QB))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"subuh_r.qb\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_addqh_ph"
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||
|
|
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_ADDQH_PH))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"addqh.ph\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_addqh_r_ph"
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||
|
|
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_ADDQH_R_PH))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"addqh_r.ph\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_addqh_w"
|
||
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
||
|
|
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
|
||
|
|
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
|
||
|
|
UNSPEC_ADDQH_W))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"addqh.w\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_addqh_r_w"
|
||
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
||
|
|
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
|
||
|
|
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
|
||
|
|
UNSPEC_ADDQH_R_W))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"addqh_r.w\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_subqh_ph"
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||
|
|
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_SUBQH_PH))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"subqh.ph\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_subqh_r_ph"
|
||
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||
|
|
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_SUBQH_R_PH))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"subqh_r.ph\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_subqh_w"
|
||
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
||
|
|
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
|
||
|
|
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
|
||
|
|
UNSPEC_SUBQH_W))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"subqh.w\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_subqh_r_w"
|
||
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
||
|
|
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
|
||
|
|
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
|
||
|
|
UNSPEC_SUBQH_R_W))]
|
||
|
|
"ISA_HAS_DSPR2"
|
||
|
|
"subqh_r.w\t%0,%z1,%z2"
|
||
|
|
[(set_attr "type" "arith")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_dpax_w_ph"
|
||
|
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
||
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_DPAX_W_PH))]
|
||
|
|
"ISA_HAS_DSPR2 && !TARGET_64BIT"
|
||
|
|
"dpax.w.ph\t%q0,%z2,%z3"
|
||
|
|
[(set_attr "type" "imadd")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_dpsx_w_ph"
|
||
|
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
||
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_DPSX_W_PH))]
|
||
|
|
"ISA_HAS_DSPR2 && !TARGET_64BIT"
|
||
|
|
"dpsx.w.ph\t%q0,%z2,%z3"
|
||
|
|
[(set_attr "type" "imadd")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_dpaqx_s_w_ph"
|
||
|
|
[(parallel
|
||
|
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
||
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_DPAQX_S_W_PH))
|
||
|
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||
|
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
||
|
|
UNSPEC_DPAQX_S_W_PH))])]
|
||
|
|
"ISA_HAS_DSPR2 && !TARGET_64BIT"
|
||
|
|
"dpaqx_s.w.ph\t%q0,%z2,%z3"
|
||
|
|
[(set_attr "type" "imadd")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_dpaqx_sa_w_ph"
|
||
|
|
[(parallel
|
||
|
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
||
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_DPAQX_SA_W_PH))
|
||
|
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||
|
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
||
|
|
UNSPEC_DPAQX_SA_W_PH))])]
|
||
|
|
"ISA_HAS_DSPR2 && !TARGET_64BIT"
|
||
|
|
"dpaqx_sa.w.ph\t%q0,%z2,%z3"
|
||
|
|
[(set_attr "type" "imadd")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_dpsqx_s_w_ph"
|
||
|
|
[(parallel
|
||
|
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
||
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_DPSQX_S_W_PH))
|
||
|
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||
|
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
||
|
|
UNSPEC_DPSQX_S_W_PH))])]
|
||
|
|
"ISA_HAS_DSPR2 && !TARGET_64BIT"
|
||
|
|
"dpsqx_s.w.ph\t%q0,%z2,%z3"
|
||
|
|
[(set_attr "type" "imadd")
|
||
|
|
(set_attr "mode" "SI")])
|
||
|
|
|
||
|
|
(define_insn "mips_dpsqx_sa_w_ph"
|
||
|
|
[(parallel
|
||
|
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
||
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||
|
|
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||
|
|
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||
|
|
UNSPEC_DPSQX_SA_W_PH))
|
||
|
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||
|
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
||
|
|
UNSPEC_DPSQX_SA_W_PH))])]
|
||
|
|
"ISA_HAS_DSPR2 && !TARGET_64BIT"
|
||
|
|
"dpsqx_sa.w.ph\t%q0,%z2,%z3"
|
||
|
|
[(set_attr "type" "imadd")
|
||
|
|
(set_attr "mode" "SI")])
|