496 lines
18 KiB
Markdown
496 lines
18 KiB
Markdown
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;; Machine description for ST Microelectronics Loongson-2E/2F.
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;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Mode iterators and attributes.
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;; 64-bit vectors of bytes.
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(define_mode_iterator VB [V8QI])
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;; 64-bit vectors of halfwords.
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(define_mode_iterator VH [V4HI])
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;; 64-bit vectors of words.
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(define_mode_iterator VW [V2SI])
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;; 64-bit vectors of halfwords and bytes.
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(define_mode_iterator VHB [V4HI V8QI])
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;; 64-bit vectors of words and halfwords.
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(define_mode_iterator VWH [V2SI V4HI])
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;; 64-bit vectors of words, halfwords and bytes.
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(define_mode_iterator VWHB [V2SI V4HI V8QI])
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;; 64-bit vectors of words, halfwords and bytes; and DImode.
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(define_mode_iterator VWHBDI [V2SI V4HI V8QI DI])
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;; The Loongson instruction suffixes corresponding to the modes in the
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;; VWHBDI iterator.
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(define_mode_attr V_suffix [(V2SI "w") (V4HI "h") (V8QI "b") (DI "d")])
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;; Given a vector type T, the mode of a vector half the size of T
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;; and with the same number of elements.
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(define_mode_attr V_squash [(V2SI "V2HI") (V4HI "V4QI")])
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;; Given a vector type T, the mode of a vector the same size as T
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;; but with half as many elements.
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(define_mode_attr V_stretch_half [(V2SI "DI") (V4HI "V2SI") (V8QI "V4HI")])
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;; The Loongson instruction suffixes corresponding to the transformation
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;; expressed by V_stretch_half.
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(define_mode_attr V_stretch_half_suffix [(V2SI "wd") (V4HI "hw") (V8QI "bh")])
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;; Given a vector type T, the mode of a vector the same size as T
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;; but with twice as many elements.
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(define_mode_attr V_squash_double [(V2SI "V4HI") (V4HI "V8QI")])
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;; The Loongson instruction suffixes corresponding to the conversions
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;; specified by V_half_width.
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(define_mode_attr V_squash_double_suffix [(V2SI "wh") (V4HI "hb")])
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;; Move patterns.
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;; Expander to legitimize moves involving values of vector modes.
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(define_expand "mov<mode>"
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[(set (match_operand:VWHB 0)
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(match_operand:VWHB 1))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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{
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if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
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DONE;
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})
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;; Handle legitimized moves between values of vector modes.
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(define_insn "mov<mode>_internal"
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[(set (match_operand:VWHB 0 "nonimmediate_operand" "=m,f,d,f, d, m, d")
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(match_operand:VWHB 1 "move_operand" "f,m,f,dYG,dYG,dYG,m"))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "fpstore,fpload,mfc,mtc,move,store,load")
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(set_attr "mode" "DI")])
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;; Initialization of a vector.
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(define_expand "vec_init<mode>"
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[(set (match_operand:VWHB 0 "register_operand")
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(match_operand 1 ""))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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{
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mips_expand_vector_init (operands[0], operands[1]);
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DONE;
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})
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;; Instruction patterns for SIMD instructions.
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;; Pack with signed saturation.
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(define_insn "vec_pack_ssat_<mode>"
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[(set (match_operand:<V_squash_double> 0 "register_operand" "=f")
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(vec_concat:<V_squash_double>
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(ss_truncate:<V_squash>
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(match_operand:VWH 1 "register_operand" "f"))
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(ss_truncate:<V_squash>
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(match_operand:VWH 2 "register_operand" "f"))))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"packss<V_squash_double_suffix>\t%0,%1,%2"
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[(set_attr "type" "fmul")])
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;; Pack with unsigned saturation.
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(define_insn "vec_pack_usat_<mode>"
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[(set (match_operand:<V_squash_double> 0 "register_operand" "=f")
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(vec_concat:<V_squash_double>
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(us_truncate:<V_squash>
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(match_operand:VH 1 "register_operand" "f"))
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(us_truncate:<V_squash>
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(match_operand:VH 2 "register_operand" "f"))))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"packus<V_squash_double_suffix>\t%0,%1,%2"
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[(set_attr "type" "fmul")])
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;; Addition, treating overflow by wraparound.
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(define_insn "add<mode>3"
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[(set (match_operand:VWHB 0 "register_operand" "=f")
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(plus:VWHB (match_operand:VWHB 1 "register_operand" "f")
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(match_operand:VWHB 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"padd<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Addition of doubleword integers stored in FP registers.
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;; Overflow is treated by wraparound.
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;; We use 'unspec' instead of 'plus' here to avoid clash with
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;; mips.md::add<mode>3. If 'plus' was used, then such instruction
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;; would be recognized as adddi3 and reload would make it use
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;; GPRs instead of FPRs.
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(define_insn "loongson_paddd"
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[(set (match_operand:DI 0 "register_operand" "=f")
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(unspec:DI [(match_operand:DI 1 "register_operand" "f")
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(match_operand:DI 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PADDD))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"paddd\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Addition, treating overflow by signed saturation.
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(define_insn "ssadd<mode>3"
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[(set (match_operand:VHB 0 "register_operand" "=f")
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(ss_plus:VHB (match_operand:VHB 1 "register_operand" "f")
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(match_operand:VHB 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"padds<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Addition, treating overflow by unsigned saturation.
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(define_insn "usadd<mode>3"
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[(set (match_operand:VHB 0 "register_operand" "=f")
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(us_plus:VHB (match_operand:VHB 1 "register_operand" "f")
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(match_operand:VHB 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"paddus<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Logical AND NOT.
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(define_insn "loongson_pandn_<V_suffix>"
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[(set (match_operand:VWHBDI 0 "register_operand" "=f")
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(and:VWHBDI
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(not:VWHBDI (match_operand:VWHBDI 1 "register_operand" "f"))
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(match_operand:VWHBDI 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pandn\t%0,%1,%2"
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[(set_attr "type" "fmul")])
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;; Average.
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(define_insn "loongson_pavg<V_suffix>"
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[(set (match_operand:VHB 0 "register_operand" "=f")
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(unspec:VHB [(match_operand:VHB 1 "register_operand" "f")
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(match_operand:VHB 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PAVG))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pavg<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Equality test.
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(define_insn "loongson_pcmpeq<V_suffix>"
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[(set (match_operand:VWHB 0 "register_operand" "=f")
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(unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f")
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(match_operand:VWHB 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PCMPEQ))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pcmpeq<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Greater-than test.
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(define_insn "loongson_pcmpgt<V_suffix>"
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[(set (match_operand:VWHB 0 "register_operand" "=f")
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(unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f")
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(match_operand:VWHB 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PCMPGT))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pcmpgt<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Extract halfword.
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(define_insn "loongson_pextr<V_suffix>"
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[(set (match_operand:VH 0 "register_operand" "=f")
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(unspec:VH [(match_operand:VH 1 "register_operand" "f")
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(match_operand:SI 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PEXTR))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pextr<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fmul")])
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;; Insert halfword.
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(define_insn "loongson_pinsr<V_suffix>_0"
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[(set (match_operand:VH 0 "register_operand" "=f")
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(unspec:VH [(match_operand:VH 1 "register_operand" "f")
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(match_operand:VH 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PINSR_0))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pinsr<V_suffix>_0\t%0,%1,%2"
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[(set_attr "type" "fdiv")])
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(define_insn "loongson_pinsr<V_suffix>_1"
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[(set (match_operand:VH 0 "register_operand" "=f")
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(unspec:VH [(match_operand:VH 1 "register_operand" "f")
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(match_operand:VH 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PINSR_1))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pinsr<V_suffix>_1\t%0,%1,%2"
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[(set_attr "type" "fdiv")])
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(define_insn "loongson_pinsr<V_suffix>_2"
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[(set (match_operand:VH 0 "register_operand" "=f")
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(unspec:VH [(match_operand:VH 1 "register_operand" "f")
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(match_operand:VH 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PINSR_2))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pinsr<V_suffix>_2\t%0,%1,%2"
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[(set_attr "type" "fdiv")])
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(define_insn "loongson_pinsr<V_suffix>_3"
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[(set (match_operand:VH 0 "register_operand" "=f")
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(unspec:VH [(match_operand:VH 1 "register_operand" "f")
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(match_operand:VH 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PINSR_3))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pinsr<V_suffix>_3\t%0,%1,%2"
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[(set_attr "type" "fdiv")])
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;; Multiply and add packed integers.
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(define_insn "loongson_pmadd<V_stretch_half_suffix>"
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[(set (match_operand:<V_stretch_half> 0 "register_operand" "=f")
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(unspec:<V_stretch_half> [(match_operand:VH 1 "register_operand" "f")
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(match_operand:VH 2 "register_operand" "f")]
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UNSPEC_LOONGSON_PMADD))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pmadd<V_stretch_half_suffix>\t%0,%1,%2"
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[(set_attr "type" "fmul")])
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;; Maximum of signed halfwords.
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(define_insn "smax<mode>3"
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[(set (match_operand:VH 0 "register_operand" "=f")
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(smax:VH (match_operand:VH 1 "register_operand" "f")
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(match_operand:VH 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pmaxs<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Maximum of unsigned bytes.
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(define_insn "umax<mode>3"
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[(set (match_operand:VB 0 "register_operand" "=f")
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(umax:VB (match_operand:VB 1 "register_operand" "f")
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(match_operand:VB 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pmaxu<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Minimum of signed halfwords.
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(define_insn "smin<mode>3"
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[(set (match_operand:VH 0 "register_operand" "=f")
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(smin:VH (match_operand:VH 1 "register_operand" "f")
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(match_operand:VH 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pmins<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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;; Minimum of unsigned bytes.
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(define_insn "umin<mode>3"
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[(set (match_operand:VB 0 "register_operand" "=f")
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(umin:VB (match_operand:VB 1 "register_operand" "f")
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(match_operand:VB 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"pminu<V_suffix>\t%0,%1,%2"
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[(set_attr "type" "fadd")])
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||
|
|
|
||
|
|
;; Move byte mask.
|
||
|
|
(define_insn "loongson_pmovmsk<V_suffix>"
|
||
|
|
[(set (match_operand:VB 0 "register_operand" "=f")
|
||
|
|
(unspec:VB [(match_operand:VB 1 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PMOVMSK))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"pmovmsk<V_suffix>\t%0,%1"
|
||
|
|
[(set_attr "type" "fabs")])
|
||
|
|
|
||
|
|
;; Multiply unsigned integers and store high result.
|
||
|
|
(define_insn "umul<mode>3_highpart"
|
||
|
|
[(set (match_operand:VH 0 "register_operand" "=f")
|
||
|
|
(unspec:VH [(match_operand:VH 1 "register_operand" "f")
|
||
|
|
(match_operand:VH 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PMULHU))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"pmulhu<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fmul")])
|
||
|
|
|
||
|
|
;; Multiply signed integers and store high result.
|
||
|
|
(define_insn "smul<mode>3_highpart"
|
||
|
|
[(set (match_operand:VH 0 "register_operand" "=f")
|
||
|
|
(unspec:VH [(match_operand:VH 1 "register_operand" "f")
|
||
|
|
(match_operand:VH 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PMULH))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"pmulh<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fmul")])
|
||
|
|
|
||
|
|
;; Multiply signed integers and store low result.
|
||
|
|
(define_insn "loongson_pmull<V_suffix>"
|
||
|
|
[(set (match_operand:VH 0 "register_operand" "=f")
|
||
|
|
(unspec:VH [(match_operand:VH 1 "register_operand" "f")
|
||
|
|
(match_operand:VH 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PMULL))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"pmull<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fmul")])
|
||
|
|
|
||
|
|
;; Multiply unsigned word integers.
|
||
|
|
(define_insn "loongson_pmulu<V_suffix>"
|
||
|
|
[(set (match_operand:DI 0 "register_operand" "=f")
|
||
|
|
(unspec:DI [(match_operand:VW 1 "register_operand" "f")
|
||
|
|
(match_operand:VW 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PMULU))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"pmulu<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fmul")])
|
||
|
|
|
||
|
|
;; Absolute difference.
|
||
|
|
(define_insn "loongson_pasubub"
|
||
|
|
[(set (match_operand:VB 0 "register_operand" "=f")
|
||
|
|
(unspec:VB [(match_operand:VB 1 "register_operand" "f")
|
||
|
|
(match_operand:VB 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PASUBUB))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"pasubub\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fadd")])
|
||
|
|
|
||
|
|
;; Sum of unsigned byte integers.
|
||
|
|
(define_insn "loongson_biadd"
|
||
|
|
[(set (match_operand:<V_stretch_half> 0 "register_operand" "=f")
|
||
|
|
(unspec:<V_stretch_half> [(match_operand:VB 1 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_BIADD))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"biadd\t%0,%1"
|
||
|
|
[(set_attr "type" "fabs")])
|
||
|
|
|
||
|
|
;; Sum of absolute differences.
|
||
|
|
(define_insn "loongson_psadbh"
|
||
|
|
[(set (match_operand:<V_stretch_half> 0 "register_operand" "=f")
|
||
|
|
(unspec:<V_stretch_half> [(match_operand:VB 1 "register_operand" "f")
|
||
|
|
(match_operand:VB 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PSADBH))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"pasubub\t%0,%1,%2;biadd\t%0,%0"
|
||
|
|
[(set_attr "type" "fadd")])
|
||
|
|
|
||
|
|
;; Shuffle halfwords.
|
||
|
|
(define_insn "loongson_pshufh"
|
||
|
|
[(set (match_operand:VH 0 "register_operand" "=f")
|
||
|
|
(unspec:VH [(match_operand:VH 1 "register_operand" "0")
|
||
|
|
(match_operand:VH 2 "register_operand" "f")
|
||
|
|
(match_operand:SI 3 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PSHUFH))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"pshufh\t%0,%2,%3"
|
||
|
|
[(set_attr "type" "fmul")])
|
||
|
|
|
||
|
|
;; Shift left logical.
|
||
|
|
(define_insn "loongson_psll<V_suffix>"
|
||
|
|
[(set (match_operand:VWH 0 "register_operand" "=f")
|
||
|
|
(ashift:VWH (match_operand:VWH 1 "register_operand" "f")
|
||
|
|
(match_operand:SI 2 "register_operand" "f")))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"psll<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fmul")])
|
||
|
|
|
||
|
|
;; Shift right arithmetic.
|
||
|
|
(define_insn "loongson_psra<V_suffix>"
|
||
|
|
[(set (match_operand:VWH 0 "register_operand" "=f")
|
||
|
|
(ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
|
||
|
|
(match_operand:SI 2 "register_operand" "f")))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"psra<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fdiv")])
|
||
|
|
|
||
|
|
;; Shift right logical.
|
||
|
|
(define_insn "loongson_psrl<V_suffix>"
|
||
|
|
[(set (match_operand:VWH 0 "register_operand" "=f")
|
||
|
|
(lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
|
||
|
|
(match_operand:SI 2 "register_operand" "f")))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"psrl<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fdiv")])
|
||
|
|
|
||
|
|
;; Subtraction, treating overflow by wraparound.
|
||
|
|
(define_insn "sub<mode>3"
|
||
|
|
[(set (match_operand:VWHB 0 "register_operand" "=f")
|
||
|
|
(minus:VWHB (match_operand:VWHB 1 "register_operand" "f")
|
||
|
|
(match_operand:VWHB 2 "register_operand" "f")))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"psub<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fadd")])
|
||
|
|
|
||
|
|
;; Subtraction of doubleword integers stored in FP registers.
|
||
|
|
;; Overflow is treated by wraparound.
|
||
|
|
;; See loongson_paddd for the reason we use 'unspec' rather than
|
||
|
|
;; 'minus' here.
|
||
|
|
(define_insn "loongson_psubd"
|
||
|
|
[(set (match_operand:DI 0 "register_operand" "=f")
|
||
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "f")
|
||
|
|
(match_operand:DI 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PSUBD))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"psubd\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fadd")])
|
||
|
|
|
||
|
|
;; Subtraction, treating overflow by signed saturation.
|
||
|
|
(define_insn "sssub<mode>3"
|
||
|
|
[(set (match_operand:VHB 0 "register_operand" "=f")
|
||
|
|
(ss_minus:VHB (match_operand:VHB 1 "register_operand" "f")
|
||
|
|
(match_operand:VHB 2 "register_operand" "f")))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"psubs<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fadd")])
|
||
|
|
|
||
|
|
;; Subtraction, treating overflow by unsigned saturation.
|
||
|
|
(define_insn "ussub<mode>3"
|
||
|
|
[(set (match_operand:VHB 0 "register_operand" "=f")
|
||
|
|
(us_minus:VHB (match_operand:VHB 1 "register_operand" "f")
|
||
|
|
(match_operand:VHB 2 "register_operand" "f")))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"psubus<V_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fadd")])
|
||
|
|
|
||
|
|
;; Unpack high data.
|
||
|
|
(define_insn "vec_interleave_high<mode>"
|
||
|
|
[(set (match_operand:VWHB 0 "register_operand" "=f")
|
||
|
|
(unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f")
|
||
|
|
(match_operand:VWHB 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PUNPCKH))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"punpckh<V_stretch_half_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fdiv")])
|
||
|
|
|
||
|
|
;; Unpack low data.
|
||
|
|
(define_insn "vec_interleave_low<mode>"
|
||
|
|
[(set (match_operand:VWHB 0 "register_operand" "=f")
|
||
|
|
(unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f")
|
||
|
|
(match_operand:VWHB 2 "register_operand" "f")]
|
||
|
|
UNSPEC_LOONGSON_PUNPCKL))]
|
||
|
|
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
|
||
|
|
"punpckl<V_stretch_half_suffix>\t%0,%1,%2"
|
||
|
|
[(set_attr "type" "fdiv")])
|
||
|
|
|
||
|
|
;; Integer division and modulus.
|
||
|
|
|
||
|
|
(define_insn "<u>div<mode>3"
|
||
|
|
[(set (match_operand:GPR 0 "register_operand" "=&d")
|
||
|
|
(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
|
||
|
|
(match_operand:GPR 2 "register_operand" "d")))]
|
||
|
|
"TARGET_LOONGSON_2EF"
|
||
|
|
{ return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands); }
|
||
|
|
[(set_attr "type" "idiv3")
|
||
|
|
(set_attr "mode" "<MODE>")])
|
||
|
|
|
||
|
|
(define_insn "<u>mod<mode>3"
|
||
|
|
[(set (match_operand:GPR 0 "register_operand" "=&d")
|
||
|
|
(any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
|
||
|
|
(match_operand:GPR 2 "register_operand" "d")))]
|
||
|
|
"TARGET_LOONGSON_2EF"
|
||
|
|
{ return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands); }
|
||
|
|
[(set_attr "type" "idiv3")
|
||
|
|
(set_attr "mode" "<MODE>")])
|