294 lines
9.7 KiB
Markdown
294 lines
9.7 KiB
Markdown
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;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005, 2007, 2008
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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; conditionals - cmp, jcc, setcc, etc.
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; Special note about conditional instructions: GCC always emits the
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; compare right before the insn, which is good, because m32c's mov
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; insns modify the flags. However, this means that any conditional
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; insn that may require reloading must be kept with its compare until
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; after reload finishes, else the reload insns might clobber the
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; flags. Thus, these rules:
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;
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; * the cmp* expanders just save the operands in compare_op0 and
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; compare_op1 via m32c_pend_compare.
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; * conditional insns that won't need reload can call
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; m32c_unpend_compare before their expansion.
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; * other insns must expand to include the compare operands within,
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; then split after reload to a separate compare and conditional.
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; Until support for relaxing is supported in gas, we must assume that
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; short labels won't reach, so we must use long labels.
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; Unfortunately, there aren't any conditional jumps with long labels,
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; so instead we invert the conditional and jump around a regular jump.
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; Note that we can, at some point in the future, add code to omit the
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; "cmp" portion of the insn if the preceding insn happened to set the
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; right flags already. For example, a mov followed by a "cmp *,0" is
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; redundant; the move already set the Z flag.
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(define_insn_and_split "cbranch<mode>4"
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[(set (pc) (if_then_else
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(match_operator 0 "m32c_cmp_operator"
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[(match_operand:QHPSI 1 "mra_operand" "RraSd")
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(match_operand:QHPSI 2 "mrai_operand" "iRraSd")])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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""
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"#"
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"reload_completed"
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[(set (reg:CC FLG_REGNO)
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(compare (match_dup 1)
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(match_dup 2)))
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(set (pc) (if_then_else (match_op_dup 0 [(reg:CC FLG_REGNO) (const_int 0)])
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(label_ref (match_dup 3))
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(pc)))]
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""
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)
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(define_insn "bcc_op"
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[(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(reg:CC FLG_REGNO) (const_int 0)])
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(label_ref (match_operand 1 ""))
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(pc)))]
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""
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"j%c0\t%l1"
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[(set_attr "flags" "n")]
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)
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(define_insn "stzx_16"
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[(set (match_operand:QI 0 "mrai_operand" "=R0w,R0w,R0w")
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(if_then_else:QI (eq (reg:CC FLG_REGNO) (const_int 0))
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(match_operand:QI 1 "const_int_operand" "i,i,0")
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(match_operand:QI 2 "const_int_operand" "i,0,i")))]
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"TARGET_A16 && reload_completed"
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"@
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stzx\t%1,%2,%0
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stz\t%1,%0
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stnz\t%2,%0"
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[(set_attr "flags" "n,n,n")]
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)
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(define_insn "stzx_24_<mode>"
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[(set (match_operand:QHI 0 "mrai_operand" "=RraSd,RraSd,RraSd")
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(if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
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(match_operand:QHI 1 "const_int_operand" "i,i,0")
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(match_operand:QHI 2 "const_int_operand" "i,0,i")))]
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"TARGET_A24 && reload_completed"
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"@
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stzx.<bwl>\t%1,%2,%0
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stz.<bwl>\t%1,%0
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stnz.<bwl>\t%2,%0"
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[(set_attr "flags" "n,n,n")])
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(define_insn_and_split "stzx_reversed_<mode>"
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[(set (match_operand:QHI 0 "m32c_r0_operand" "=R0w")
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(if_then_else:QHI (ne (reg:CC FLG_REGNO) (const_int 0))
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(match_operand:QHI 1 "const_int_operand" "")
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(match_operand:QHI 2 "const_int_operand" "")))]
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"(TARGET_A24 || GET_MODE (operands[0]) == QImode) && reload_completed"
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"#"
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""
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[(set (match_dup 0)
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(if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
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(match_dup 2)
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(match_dup 1)))]
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""
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)
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(define_insn "cmp<mode>_op"
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[(set (reg:CC FLG_REGNO)
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(compare (match_operand:QHPSI 0 "mra_operand" "RraSd")
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(match_operand:QHPSI 1 "mrai_operand" "RraSdi")))]
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""
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"* return m32c_output_compare(insn, operands); "
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[(set_attr "flags" "oszc")])
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;; m32c_conditional_register_usage changes the setcc_gen_code array to
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;; point to the _24 variants if needed.
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;; We need to keep the compare and conditional sets together through
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;; reload, because reload might need to add address reloads to the
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;; set, which would clobber the flags. By keeping them together, the
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;; reloads get put before the compare, thus preserving the flags.
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;; These are the post-split patterns for the conditional sets.
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(define_insn "scc_op"
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[(set (match_operand:QI 0 "register_operand" "=Rqi")
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(match_operator:QI 1 "ordered_comparison_operator"
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[(reg:CC FLG_REGNO) (const_int 0)]))]
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"TARGET_A16 && reload_completed"
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"* return m32c_scc_pattern(operands, GET_CODE (operands[1]));")
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(define_insn "scc_24_op"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd")
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(match_operator:HI 1 "ordered_comparison_operator"
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[(reg:CC FLG_REGNO) (const_int 0)]))]
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"TARGET_A24 && reload_completed"
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"sc%c1\t%0"
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[(set_attr "flags" "n")]
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)
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;; These are the pre-split patterns for the conditional sets.
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(define_insn_and_split "cstore<mode>4"
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[(set (match_operand:QI 0 "register_operand" "=Rqi")
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(match_operator:QI 1 "ordered_comparison_operator"
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[(match_operand:QHPSI 2 "mra_operand" "RraSd")
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(match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
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"TARGET_A16"
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"#"
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"reload_completed"
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[(set (reg:CC FLG_REGNO)
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(compare (match_dup 2)
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(match_dup 3)))
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(set (match_dup 0)
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(match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]
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""
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[(set_attr "flags" "x")]
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)
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(define_insn_and_split "cstore<mode>4_24"
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[(set (match_operand:HI 0 "mra_nopp_operand" "=RhiSd")
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(match_operator:HI 1 "ordered_comparison_operator"
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[(match_operand:QHPSI 2 "mra_operand" "RraSd")
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(match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
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"TARGET_A24"
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"#"
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"reload_completed"
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[(set (reg:CC FLG_REGNO)
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(compare (match_dup 2)
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(match_dup 3)))
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(set (match_dup 0)
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(match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]
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""
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[(set_attr "flags" "x")]
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)
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(define_insn_and_split "movqicc_<code>_<mode>"
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[(set (match_operand:QI 0 "register_operand" "=R0w")
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(if_then_else:QI (eqne_cond:QI (match_operand:QHPSI 1 "mra_operand" "RraSd")
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(match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
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(match_operand:QI 3 "const_int_operand" "")
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(match_operand:QI 4 "const_int_operand" "")))]
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""
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"#"
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"reload_completed"
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[(set (reg:CC FLG_REGNO)
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(compare (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(if_then_else:QI (eqne_cond:QI (reg:CC FLG_REGNO) (const_int 0))
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(match_dup 3)
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(match_dup 4)))]
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""
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[(set_attr "flags" "x")]
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)
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(define_insn_and_split "movhicc_<code>_<mode>"
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[(set (match_operand:HI 0 "register_operand" "=R0w")
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(if_then_else:HI (eqne_cond:HI (match_operand:QHPSI 1 "mra_operand" "RraSd")
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(match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
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(match_operand:QI 3 "const_int_operand" "")
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(match_operand:QI 4 "const_int_operand" "")))]
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"TARGET_A24"
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"#"
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"reload_completed"
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[(set (reg:CC FLG_REGNO)
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(compare (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(if_then_else:HI (eqne_cond:HI (reg:CC FLG_REGNO) (const_int 0))
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(match_dup 3)
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(match_dup 4)))]
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""
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[(set_attr "flags" "x")]
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)
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;; And these are the expanders.
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(define_expand "movqicc"
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[(set (match_operand:QI 0 "register_operand" "")
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(if_then_else:QI (match_operand 1 "m32c_eqne_operator" "")
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(match_operand:QI 2 "const_int_operand" "")
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(match_operand:QI 3 "const_int_operand" "")))]
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""
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"if (m32c_expand_movcc(operands))
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FAIL;
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DONE;"
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)
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(define_expand "movhicc"
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[(set (match_operand:HI 0 "mra_operand" "")
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(if_then_else:HI (match_operand 1 "m32c_eqne_operator" "")
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(match_operand:HI 2 "const_int_operand" "")
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(match_operand:HI 3 "const_int_operand" "")))]
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"TARGET_A24"
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"if (m32c_expand_movcc(operands))
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FAIL;
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DONE;"
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)
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;; CMP opcodes subtract two values, set the flags, and discard the
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;; value. This pattern recovers the sign of the discarded value based
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;; on the flags. Operand 0 is set to -1, 0, or 1. This is used for
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;; the cmpstr pattern. For optimal code, this should be removed if
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;; followed by a suitable CMP insn (see the peephole following). This
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;; pattern is 7 bytes and 5 cycles. If you don't need specific
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;; values, a 5/4 pattern can be made with SCGT and BMLT to set the
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;; appropriate bits.
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(define_insn "cond_to_int"
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[(set (match_operand:HI 0 "mra_qi_operand" "=Rqi")
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(if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))
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(const_int -1)
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(if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))
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(const_int 0)
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(const_int -1))))]
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"TARGET_A24"
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"sceq\t%0\n\tbmgt\t1,%h0\n\tdec.w\t%0"
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[(set_attr "flags" "x")]
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)
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;; A cond_to_int followed by a compare against zero is essentially a
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;; no-op. However, the result of the cond_to_int may be used by later
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;; insns, so make sure it's dead before deleting its set.
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(define_peephole2
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[(set (match_operand:HI 0 "mra_qi_operand" "")
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(if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))
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(const_int -1)
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(if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))
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(const_int 0)
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(const_int -1))))
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(set (reg:CC FLG_REGNO)
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(compare (match_operand:HI 1 "mra_qi_operand" "")
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(const_int 0)))
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]
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"rtx_equal_p (operands[0], operands[1])
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&& dead_or_set_p (peep2_next_insn (1), operands[0])"
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[(const_int 1)]
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"")
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