243 lines
7.4 KiB
Markdown
243 lines
7.4 KiB
Markdown
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;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2006, 2007
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; various block move instructions
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;; R8C:
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;; SMOVB - while (r3--) { *a1-- = *r1ha0--; } - memcpy
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;; SMOVF - while (r3--) { *a1++ = *r1ha0++; } - memcpy
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;; SSTR - while (r3--) { *a1++ = [r0l,r0]; } - memset
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;; M32CM:
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;; SCMPU - while (*a0 && *a0 != *a1) { a0++; a1++; } - strcmp
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;; SIN - while (r3--) { *a1++ = *a0; }
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;; SMOVB - while (r3--) { *a1-- = *a0--; } - memcpy
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;; SMOVF - while (r3--) { *a1++ = *a0++; } - memcpy
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;; SMOVU - while (*a1++ = *a0++) ; - strcpy
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;; SOUT - while (r3--) { *a1 = *a0++; }
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;; SSTR - while (r3--) { *a1++ = [r0l,r0]; } - memset
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;; 0 = destination (mem:BLK ...)
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;; 1 = source (mem:BLK ...)
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;; 2 = count
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;; 3 = alignment
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(define_expand "movmemhi"
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[(match_operand 0 "ap_operand" "")
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(match_operand 1 "ap_operand" "")
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(match_operand 2 "m32c_r3_operand" "")
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(match_operand 3 "" "")
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]
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""
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"if (m32c_expand_movmemhi(operands)) DONE; FAIL;"
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)
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;; We can't use mode iterators for these because M16C uses r1h to extend
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;; the source address, for copying data from ROM to RAM. We don't yet
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;; support that, but we need to zero our r1h, so the patterns differ.
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;; 0 = dest (out)
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;; 1 = src (out)
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;; 2 = count (out)
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;; 3 = dest (in)
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;; 4 = src (in)
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;; 5 = count (in)
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(define_insn "movmemhi_bhi_op"
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[(set (mem:QI (match_operand:HI 3 "ap_operand" "0"))
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(mem:QI (match_operand:HI 4 "ap_operand" "1")))
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(set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
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(const_int 0))
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(set (match_operand:HI 0 "ap_operand" "=Ra1")
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(plus:HI (match_dup 3)
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(zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
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(set (match_operand:HI 1 "ap_operand" "=Ra0")
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(plus:HI (match_dup 4)
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(zero_extend:HI (match_dup 5))))
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(use (reg:HI R1_REGNO))]
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"TARGET_A16"
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"mov.b:q\t#0,r1h\n\tsmovf.b\t; %0[0..%2-1]=r1h%1[]"
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)
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(define_insn "movmemhi_bpsi_op"
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[(set (mem:QI (match_operand:PSI 3 "ap_operand" "0"))
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(mem:QI (match_operand:PSI 4 "ap_operand" "1")))
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(set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
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(const_int 0))
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(set (match_operand:PSI 0 "ap_operand" "=Ra1")
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(plus:PSI (match_dup 3)
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(zero_extend:PSI (match_operand:HI 5 "m32c_r3_operand" "2"))))
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(set (match_operand:PSI 1 "ap_operand" "=Ra0")
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(plus:PSI (match_dup 4)
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(zero_extend:PSI (match_dup 5))))]
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"TARGET_A24"
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"smovf.b\t; %0[0..%2-1]=%1[]"
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)
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(define_insn "movmemhi_whi_op"
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[(set (mem:HI (match_operand:HI 3 "ap_operand" "0"))
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(mem:HI (match_operand:HI 4 "ap_operand" "1")))
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(set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
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(const_int 0))
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(set (match_operand:HI 0 "ap_operand" "=Ra1")
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(plus:HI (match_dup 3)
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(zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
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(set (match_operand:HI 1 "ap_operand" "=Ra0")
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(plus:HI (match_dup 4)
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(zero_extend:HI (match_dup 5))))
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(use (reg:HI R1_REGNO))]
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"TARGET_A16"
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"mov.b:q\t#0,r1h\n\tsmovf.w\t; %0[0..%2-1]=r1h%1[]"
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)
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(define_insn "movmemhi_wpsi_op"
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[(set (mem:HI (match_operand:PSI 3 "ap_operand" "0"))
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(mem:HI (match_operand:PSI 4 "ap_operand" "1")))
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(set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
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(const_int 0))
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(set (match_operand:PSI 0 "ap_operand" "=Ra1")
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(plus:PSI (match_dup 3)
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(zero_extend:PSI (match_operand:HI 5 "m32c_r3_operand" "2"))))
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(set (match_operand:PSI 1 "ap_operand" "=Ra0")
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(plus:PSI (match_dup 4)
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(zero_extend:PSI (match_dup 5))))]
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"TARGET_A24"
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"smovf.w\t; %0[0..%2-1]=%1[]"
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)
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;; 0 = destination (mem:BLK ...)
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;; 1 = number of bytes
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;; 2 = value to store
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;; 3 = alignment
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(define_expand "setmemhi"
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[(match_operand 0 "ap_operand" "")
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(match_operand 1 "m32c_r3_operand" "")
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(match_operand 2 "m32c_r0_operand" "")
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(match_operand 3 "" "")
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]
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"TARGET_A24"
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"if (m32c_expand_setmemhi(operands)) DONE; FAIL;"
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)
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;; 0 = address (out)
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;; 1 = count (out)
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;; 2 = value (in)
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;; 3 = address (in)
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;; 4 = count (in)
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(define_insn "setmemhi_b<mode>_op"
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[(set (mem:QI (match_operand:HPSI 3 "ap_operand" "0"))
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(match_operand:QI 2 "m32c_r0_operand" "R0w"))
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(set (match_operand:HI 1 "m32c_r3_operand" "=R3w")
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(const_int 0))
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(set (match_operand:HPSI 0 "ap_operand" "=Ra1")
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(plus:HPSI (match_dup 3)
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(zero_extend:HPSI (match_operand:HI 4 "m32c_r3_operand" "1"))))]
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"TARGET_A24"
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"sstr.b\t; %0[0..%1-1]=%2"
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)
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(define_insn "setmemhi_w<mode>_op"
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[(set (mem:HI (match_operand:HPSI 3 "ap_operand" "0"))
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(match_operand:HI 2 "m32c_r0_operand" "R0w"))
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(set (match_operand:HI 1 "m32c_r3_operand" "=R3w")
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(const_int 0))
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(set (match_operand:HPSI 0 "ap_operand" "=Ra1")
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(plus:HPSI (match_dup 3)
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(zero_extend:HPSI (match_operand:HI 4 "m32c_r3_operand" "1"))))]
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"TARGET_A24"
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"sstr.w\t; %0[0..%1-1]=%2"
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)
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;; SCMPU sets the flags according to the result of the string
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;; comparison. GCC wants the result to be a signed value reflecting
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;; the result, which it then compares to zero. Hopefully we can
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;; optimize that later (see peephole in cond.md). Meanwhile, the
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;; strcmp builtin is expanded to a SCMPU followed by a flags-to-int
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;; pattern in cond.md.
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;; 0 = result:HI
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;; 1 = destination (mem:BLK ...)
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;; 2 = source (mem:BLK ...)
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;; 3 = alignment
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(define_expand "cmpstrsi"
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[(match_operand:HI 0 "" "")
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(match_operand 1 "ap_operand" "")
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(match_operand 2 "ap_operand" "")
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(match_operand 3 "" "")
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]
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"TARGET_A24"
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"if (m32c_expand_cmpstr(operands)) DONE; FAIL;"
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)
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;; 0 = string1
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;; 1 = string2
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(define_insn "cmpstrhi_op"
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[(set (reg:CC FLG_REGNO)
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(compare:CC (mem:BLK (match_operand:PSI 0 "ap_operand" "Ra0"))
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(mem:BLK (match_operand:PSI 1 "ap_operand" "Ra1"))))
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(clobber (match_operand:PSI 2 "ap_operand" "=0"))
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(clobber (match_operand:PSI 3 "ap_operand" "=1"))]
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"TARGET_A24"
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"scmpu.b\t; flags := strcmp(*%0,*%1)"
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[(set_attr "flags" "oszc")]
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)
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;; Note that SMOVU leaves the address registers pointing *after*
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;; the NUL at the end of the string. This is not what gcc expects; it
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;; expects the address registers to point *at* the NUL. The expander
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;; must emit a suitable add insn.
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;; 0 = target: set to &NUL in dest
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;; 1 = destination (mem:BLK ...)
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;; 2 = source (mem:BLK ...)
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(define_expand "movstr"
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[(match_operand 0 "" "")
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(match_operand 1 "ap_operand" "")
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(match_operand 2 "ap_operand" "")
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]
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"TARGET_A24"
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"if (m32c_expand_movstr(operands)) DONE; FAIL;"
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)
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;; 0 = dest (out)
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;; 1 = src (out) (clobbered)
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;; 2 = dest (in)
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;; 3 = src (in)
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(define_insn "movstr_op"
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[(set (mem:BLK (match_operand:PSI 2 "ap_operand" "0"))
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(mem:BLK (match_operand:PSI 3 "ap_operand" "1")))
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(set (match_operand:PSI 0 "ap_operand" "=Ra1")
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(plus:PSI (match_dup 2)
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(unspec:PSI [(const_int 0)] UNS_SMOVU)))
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(set (match_operand:PSI 1 "ap_operand" "=Ra0")
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(plus:PSI (match_dup 3)
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(unspec:PSI [(const_int 0)] UNS_SMOVU)))]
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"TARGET_A24"
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"smovu.b\t; while (*%2++ := *%3++) != 0"
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[(set_attr "flags" "*")]
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)
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