268 lines
9.8 KiB
Markdown
268 lines
9.8 KiB
Markdown
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;; AMD K6/K6-2 Scheduling
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;; Copyright (C) 2002, 2004, 2007
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;
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;; The K6 architecture is quite similar to PPro. Important difference is
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;; that there are only two decoders and they seems to be much slower than
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;; any of the execution units. So we have to pay much more attention to
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;; proper scheduling for the decoders.
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;; FIXME: We don't do that right now. A good start would be to sort the
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;; instructions based on length.
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;;
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;; This description is based on data from the following documents:
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;;
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;; "AMD-K6 Processor Data Sheet (Preliminary information)"
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;; Advanced Micro Devices, Inc., 1998.
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;;
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;; "AMD-K6 Processor Code Optimization Application Note"
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;; Advanced Micro Devices, Inc., 2000.
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;;
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;; CPU execution units of the K6:
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;;
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;; store describes the Store unit. This unit is not modelled
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;; completely and it is only used to model lea operation.
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;; Otherwise it lies outside of any critical path.
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;; load describes the Load unit
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;; alux describes the Integer X unit
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;; mm describes the Multimedia unit, which shares a pipe
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;; with the Integer X unit. This unit is used for MMX,
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;; which is not implemented for K6.
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;; aluy describes the Integer Y unit
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;; fpu describes the FPU unit
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;; branch describes the Branch unit
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;;
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;; The fp unit is not pipelined, and it can only do one operation per two
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;; cycles, including fxcg.
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;;
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;; Generally this is a very poor description, but at least no worse than
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;; the old description, and a lot easier to extend to something more
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;; reasonable if anyone still cares enough about this architecture in 2004.
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;;
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;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
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(define_automaton "k6_decoder,k6_load_unit,k6_store_unit,k6_integer_units,k6_fpu_unit,k6_branch_unit")
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;; The K6 instruction decoding begins before the on-chip instruction cache is
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;; filled. Depending on the length of the instruction, two simple instructions
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;; can be decoded in two parallel short decoders, or one complex instruction can
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;; be decoded in either the long or the vector decoder. For all practical
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;; purposes, the long and vector decoder can be modelled as one decoder.
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(define_cpu_unit "k6_decode_short0" "k6_decoder")
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(define_cpu_unit "k6_decode_short1" "k6_decoder")
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(define_cpu_unit "k6_decode_long" "k6_decoder")
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(exclusion_set "k6_decode_long" "k6_decode_short0,k6_decode_short1")
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(define_reservation "k6_decode_short" "k6_decode_short0|k6_decode_short1")
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(define_reservation "k6_decode_vector" "k6_decode_long")
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(define_cpu_unit "k6_store" "k6_store_unit")
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(define_cpu_unit "k6_load" "k6_load_unit")
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(define_cpu_unit "k6_alux,k6_aluy" "k6_integer_units")
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(define_cpu_unit "k6_fpu" "k6_fpu_unit")
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(define_cpu_unit "k6_branch" "k6_branch_unit")
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;; Shift instructions and certain arithmetic are issued only on Integer X.
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(define_insn_reservation "k6_alux_only" 1
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot")
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(eq_attr "memory" "none")))
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"k6_decode_short,k6_alux")
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(define_insn_reservation "k6_alux_only_load" 3
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot")
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(eq_attr "memory" "load")))
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"k6_decode_short,k6_load,k6_alux")
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(define_insn_reservation "k6_alux_only_store" 3
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot")
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(eq_attr "memory" "store,both,unknown")))
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"k6_decode_long,k6_load,k6_alux,k6_store")
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;; Integer divide and multiply can only be issued on Integer X, too.
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(define_insn_reservation "k6_alu_imul" 2
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "imul"))
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"k6_decode_vector,k6_alux*3")
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(define_insn_reservation "k6_alu_imul_load" 4
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "imul")
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(eq_attr "memory" "load")))
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"k6_decode_vector,k6_load,k6_alux*3")
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(define_insn_reservation "k6_alu_imul_store" 4
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "imul")
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(eq_attr "memory" "store,both,unknown")))
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"k6_decode_vector,k6_load,k6_alux*3,k6_store")
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;; ??? Guessed latencies based on the old pipeline description.
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(define_insn_reservation "k6_alu_idiv" 17
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "idiv")
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(eq_attr "memory" "none")))
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"k6_decode_vector,k6_alux*17")
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(define_insn_reservation "k6_alu_idiv_mem" 19
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "idiv")
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(eq_attr "memory" "!none")))
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"k6_decode_vector,k6_load,k6_alux*17")
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;; Basic word and doubleword ALU ops can be issued on both Integer units.
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(define_insn_reservation "k6_alu" 1
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
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(eq_attr "memory" "none")))
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"k6_decode_short,k6_alux|k6_aluy")
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(define_insn_reservation "k6_alu_load" 3
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
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(eq_attr "memory" "load")))
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"k6_decode_short,k6_load,k6_alux|k6_aluy")
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(define_insn_reservation "k6_alu_store" 3
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
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(eq_attr "memory" "store,both,unknown")))
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"k6_decode_long,k6_load,k6_alux|k6_aluy,k6_store")
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;; A "load immediate" operation does not require execution at all,
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;; it is available immediately after decoding. Special-case this.
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(define_insn_reservation "k6_alu_imov" 1
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "imov")
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(and (eq_attr "memory" "none")
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(match_operand 1 "nonimmediate_operand"))))
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"k6_decode_short,k6_alux|k6_aluy")
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(define_insn_reservation "k6_alu_imov_imm" 0
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "imov")
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(and (eq_attr "memory" "none")
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(match_operand 1 "immediate_operand"))))
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"k6_decode_short")
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(define_insn_reservation "k6_alu_imov_load" 2
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "load")))
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"k6_decode_short,k6_load")
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(define_insn_reservation "k6_alu_imov_store" 1
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "store")))
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"k6_decode_short,k6_store")
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(define_insn_reservation "k6_alu_imov_both" 2
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "both,unknown")))
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"k6_decode_long,k6_load,k6_alux|k6_aluy")
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;; The branch unit.
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(define_insn_reservation "k6_branch_call" 1
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "call,callv"))
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"k6_decode_vector,k6_branch")
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(define_insn_reservation "k6_branch_branch" 1
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "ibr"))
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"k6_decode_short,k6_branch")
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;; The load and units have two pipeline stages. The load latency is
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;; two cycles.
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(define_insn_reservation "k6_load_pop" 3
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(and (eq_attr "cpu" "k6")
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(ior (eq_attr "type" "pop")
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(eq_attr "memory" "load,both")))
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"k6_decode_short,k6_load")
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(define_insn_reservation "k6_load_leave" 5
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "leave"))
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"k6_decode_long,k6_load,(k6_alux|k6_aluy)*2")
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;; ??? From the old pipeline description. Egad!
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;; ??? Apparently we take care of this reservation in adjust_cost.
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(define_insn_reservation "k6_load_str" 10
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "str")
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(eq_attr "memory" "load,both")))
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"k6_decode_vector,k6_load*10")
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;; The store unit handles lea and push. It is otherwise unmodelled.
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(define_insn_reservation "k6_store_lea" 2
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "lea"))
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"k6_decode_short,k6_store,k6_alux|k6_aluy")
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(define_insn_reservation "k6_store_push" 2
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(and (eq_attr "cpu" "k6")
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(ior (eq_attr "type" "push")
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(eq_attr "memory" "store,both")))
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"k6_decode_short,k6_store")
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(define_insn_reservation "k6_store_str" 10
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "str"))
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"k6_store*10")
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;; Most FPU instructions have latency 2 and throughput 2.
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(define_insn_reservation "k6_fpu" 2
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "fop,fmov,fcmp,fistp")
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(eq_attr "memory" "none")))
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"k6_decode_vector,k6_fpu*2")
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(define_insn_reservation "k6_fpu_load" 6
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "fop,fmov,fcmp,fistp")
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(eq_attr "memory" "load,both")))
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"k6_decode_short,k6_load,k6_fpu*2")
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(define_insn_reservation "k6_fpu_store" 6
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "fop,fmov,fcmp,fistp")
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(eq_attr "memory" "store")))
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"k6_decode_short,k6_store,k6_fpu*2")
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(define_insn_reservation "k6_fpu_fmul" 2
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "fmul")
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(eq_attr "memory" "none")))
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"k6_decode_short,k6_fpu*2")
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(define_insn_reservation "k6_fpu_fmul_load" 2
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "fmul")
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(eq_attr "memory" "load,both")))
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"k6_decode_short,k6_load,k6_fpu*2")
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;; ??? Guessed latencies from the old pipeline description.
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(define_insn_reservation "k6_fpu_expensive" 56
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "fdiv,fpspc"))
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"k6_decode_short,k6_fpu*56")
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