162 lines
5.1 KiB
Markdown
162 lines
5.1 KiB
Markdown
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;; ARM Cortex-R4F VFP pipeline description
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;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
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;; Written by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; With the exception of simple VMOV <freg>, <freg> instructions and
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;; the accululate operand of a multiply-accumulate instruction, all
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;; registers are early registers. Thus base latencies are 1 more than
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;; those listed in the TRM.
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;; We use the A, B abd C units from the integer core, plus two additional
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;; units to enforce VFP dual issue constraints.
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;; A B C V1 VMLA
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;; fcpy 1 2
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;; farith 1 2 1
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;; fmrc 1 2
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;; fconst 1 2 * *
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;; ffarith 1 2 * *
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;; fmac 1 2 1 2
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;; fdiv 1 2 *
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;; f_loads * * *
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;; f_stores * * *
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(define_cpu_unit "cortex_r4_v1" "cortex_r4")
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(define_cpu_unit "cortex_r4_vmla" "cortex_r4")
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(define_reservation "cortex_r4_issue_ab"
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"(cortex_r4_issue_a|cortex_r4_issue_b)")
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(define_reservation "cortex_r4_single_issue"
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"cortex_r4_issue_a+cortex_r4_issue_b")
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(define_insn_reservation "cortex_r4_fcpys" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "fcpys"))
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"cortex_r4_issue_ab")
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(define_insn_reservation "cortex_r4_ffariths" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "ffariths,fconsts,fcmps"))
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"cortex_r4_issue_ab+cortex_r4_issue_c+cortex_r4_v1")
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(define_insn_reservation "cortex_r4_fariths" 3
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "fadds,fmuls"))
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"(cortex_r4_issue_a+cortex_r4_v1)|cortex_r4_issue_b")
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(define_insn_reservation "cortex_r4_fmacs" 6
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "fmacs"))
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"(cortex_r4_issue_a+cortex_r4_v1)|(cortex_r4_issue_b+cortex_r4_vmla)")
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(define_insn_reservation "cortex_r4_fdivs" 17
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "fdivs"))
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"cortex_r4_issue_ab+cortex_r4_v1,cortex_r4_issue_a+cortex_r4_v1")
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(define_insn_reservation "cortex_r4_floads" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "f_loads"))
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"cortex_r4_issue_a+cortex_r4_issue_c+cortex_r4_v1")
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(define_insn_reservation "cortex_r4_fstores" 1
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "f_stores"))
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"cortex_r4_issue_a+cortex_r4_issue_c+cortex_r4_vmla")
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(define_insn_reservation "cortex_r4_mcr" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "r_2_f"))
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"cortex_r4_issue_ab")
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(define_insn_reservation "cortex_r4_mrc" 3
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "f_2_r"))
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"cortex_r4_issue_ab")
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;; Bypasses for normal (not early) regs.
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(define_bypass 1 "cortex_r4_ffariths,cortex_r4_fcpys,cortex_r4_mcr"
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"cortex_r4_fcpys")
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(define_bypass 2 "cortex_r4_fariths"
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"cortex_r4_fcpys")
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(define_bypass 5 "cortex_r4_fmacs"
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"cortex_r4_fcpys")
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(define_bypass 16 "cortex_r4_fdivs"
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"cortex_r4_fcpys")
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(define_bypass 1 "cortex_r4_ffariths,cortex_r4_fcpys,cortex_r4_mcr"
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"cortex_r4_fmacs"
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"arm_no_early_mul_dep")
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(define_bypass 2 "cortex_r4_fariths"
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"cortex_r4_fmacs"
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"arm_no_early_mul_dep")
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;; mac->mac has an extra forwarding path.
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(define_bypass 3 "cortex_r4_fmacs"
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"cortex_r4_fmacs"
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"arm_no_early_mul_dep")
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(define_bypass 16 "cortex_r4_fdivs"
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"cortex_r4_fmacs"
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"arm_no_early_mul_dep")
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;; Double precision operations. These can not dual issue.
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(define_insn_reservation "cortex_r4_fmacd" 20
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "fmacd"))
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"cortex_r4_single_issue*13")
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(define_insn_reservation "cortex_r4_farith" 10
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "faddd,fmuld"))
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"cortex_r4_single_issue*3")
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;; FIXME: The short cycle count suggests these instructions complete
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;; out of order. Chances are this is not a pipelined operation.
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(define_insn_reservation "cortex_r4_fdivd" 97
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "fdivd"))
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"cortex_r4_single_issue*3")
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(define_insn_reservation "cortex_r4_ffarithd" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "ffarithd,fconstd"))
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"cortex_r4_single_issue")
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(define_insn_reservation "cortex_r4_fcmpd" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "fcmpd"))
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"cortex_r4_single_issue*2")
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(define_insn_reservation "cortex_r4_f_cvt" 8
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "f_cvt"))
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"cortex_r4_single_issue*3")
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(define_insn_reservation "cortex_r4_f_memd" 8
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "f_loadd,f_stored"))
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"cortex_r4_single_issue")
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(define_insn_reservation "cortex_r4_f_flag" 1
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "f_stores"))
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"cortex_r4_single_issue")
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