195 lines
6.2 KiB
Markdown
195 lines
6.2 KiB
Markdown
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;; Scheduling description for Alpha EV5.
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;; Copyright (C) 2002, 2004, 2005, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; EV5 has two asymmetric integer units, E0 and E1, plus separate
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;; FP add and multiply units.
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(define_automaton "ev5_0,ev5_1")
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(define_cpu_unit "ev5_e0,ev5_e1,ev5_fa,ev5_fm" "ev5_0")
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(define_reservation "ev5_e01" "ev5_e0|ev5_e1")
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(define_reservation "ev5_fam" "ev5_fa|ev5_fm")
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(define_cpu_unit "ev5_imul" "ev5_0")
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(define_cpu_unit "ev5_fdiv" "ev5_1")
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; Assume type "multi" single issues.
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(define_insn_reservation "ev5_multi" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "multi"))
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"ev5_e0+ev5_e1+ev5_fa+ev5_fm")
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; Stores can only issue to E0, and may not issue with loads.
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; Model this with some fake units.
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(define_cpu_unit "ev5_l0,ev5_l1,ev5_st" "ev5_0")
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(define_reservation "ev5_ld" "ev5_l0|ev5_l1")
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(exclusion_set "ev5_l0,ev5_l1" "ev5_st")
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(define_insn_reservation "ev5_st" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "ist,fst,st_c,mb"))
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"ev5_e0+ev5_st")
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; Loads from L0 complete in two cycles. adjust_cost still factors
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; in user-specified memory latency, so return 1 here.
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(define_insn_reservation "ev5_ld" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "ild,fld,ldsym"))
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"ev5_e01+ev5_ld")
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(define_insn_reservation "ev5_ld_l" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "ld_l"))
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"ev5_e0+ev5_ld")
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; Integer branches slot only to E1.
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(define_insn_reservation "ev5_ibr" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "ibr"))
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"ev5_e1")
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(define_insn_reservation "ev5_callpal" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "callpal"))
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"ev5_e1")
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(define_insn_reservation "ev5_jsr" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "jsr"))
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"ev5_e1")
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(define_insn_reservation "ev5_shift" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "shift"))
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"ev5_e0")
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(define_insn_reservation "ev5_mvi" 2
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "mvi"))
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"ev5_e0")
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(define_insn_reservation "ev5_cmov" 2
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "icmov"))
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"ev5_e01")
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(define_insn_reservation "ev5_iadd" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "iadd"))
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"ev5_e01")
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(define_insn_reservation "ev5_ilogcmp" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "ilog,icmp"))
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"ev5_e01")
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; Conditional move and branch can issue the same cycle as the test.
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(define_bypass 0 "ev5_ilogcmp" "ev5_ibr,ev5_cmov" "if_test_bypass_p")
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; Multiplies use a non-pipelined imul unit. Also, "no insn can be issued
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; to E0 exactly two cycles before an integer multiply completes".
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(define_insn_reservation "ev5_imull" 8
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(and (eq_attr "tune" "ev5")
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(and (eq_attr "type" "imul")
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(eq_attr "opsize" "si")))
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"ev5_e0+ev5_imul,ev5_imul*3,nothing,ev5_e0")
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(define_insn_reservation "ev5_imulq" 12
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(and (eq_attr "tune" "ev5")
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(and (eq_attr "type" "imul")
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(eq_attr "opsize" "di")))
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"ev5_e0+ev5_imul,ev5_imul*7,nothing,ev5_e0")
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(define_insn_reservation "ev5_imulh" 14
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(and (eq_attr "tune" "ev5")
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(and (eq_attr "type" "imul")
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(eq_attr "opsize" "udi")))
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"ev5_e0+ev5_imul,ev5_imul*7,nothing*3,ev5_e0")
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; The multiplier is unable to receive data from Ebox bypass paths. The
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; instruction issues at the expected time, but its latency is increased
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; by the time it takes for the input data to become available to the
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; multiplier. For example, an IMULL instruction issued one cycle later
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; than an ADDL instruction, which produced one of its operands, has a
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; latency of 10 (8 + 2). If the IMULL instruction is issued two cycles
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; later than the ADDL instruction, the latency is 9 (8 + 1).
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;
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; Model this instead with increased latency on the input instruction.
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(define_bypass 3
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"ev5_ld,ev5_ld_l,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
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"ev5_imull,ev5_imulq,ev5_imulh")
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(define_bypass 9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh")
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(define_bypass 13 "ev5_imulq" "ev5_imull,ev5_imulq,ev5_imulh")
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(define_bypass 15 "ev5_imulh" "ev5_imull,ev5_imulq,ev5_imulh")
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; Similarly for the FPU we have two asymmetric units.
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(define_insn_reservation "ev5_fadd" 4
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "fadd,fcmov"))
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"ev5_fa")
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(define_insn_reservation "ev5_fbr" 1
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "fbr"))
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"ev5_fa")
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(define_insn_reservation "ev5_fcpys" 4
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "fcpys"))
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"ev5_fam")
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(define_insn_reservation "ev5_fmul" 4
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "fmul"))
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"ev5_fm")
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; The floating point divider is not pipelined. Also, "no insn can be issued
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; to FA exactly five before an fdiv insn completes".
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;
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; ??? Do not model this late reservation due to the enormously increased
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; size of the resulting DFA.
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;
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; ??? Putting ev5_fa and ev5_fdiv alone into the same automata produces
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; a DFA of acceptable size, but putting ev5_fm and ev5_fa into separate
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; automata produces incorrect results for insns that can choose one or
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; the other, i.e. ev5_fcpys.
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(define_insn_reservation "ev5_fdivsf" 15
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(and (eq_attr "tune" "ev5")
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(and (eq_attr "type" "fdiv")
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(eq_attr "opsize" "si")))
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; "ev5_fa+ev5_fdiv,ev5_fdiv*9,ev5_fa+ev5_fdiv,ev5_fdiv*4"
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"ev5_fa+ev5_fdiv,ev5_fdiv*14")
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(define_insn_reservation "ev5_fdivdf" 22
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(and (eq_attr "tune" "ev5")
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(and (eq_attr "type" "fdiv")
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(eq_attr "opsize" "di")))
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; "ev5_fa+ev5_fdiv,ev5_fdiv*17,ev5_fa+ev5_fdiv,ev5_fdiv*4"
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"ev5_fa+ev5_fdiv,ev5_fdiv*21")
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; Traps don't consume or produce data; rpcc is latency 2 if we ever add it.
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(define_insn_reservation "ev5_misc" 2
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(and (eq_attr "tune" "ev5")
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(eq_attr "type" "misc"))
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"ev5_e0")
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