200 lines
6.2 KiB
Markdown
200 lines
6.2 KiB
Markdown
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;; GCC machine description for SPARC synchronization instructions.
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;; Copyright (C) 2005, 2007, 2009
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_mode_iterator I12MODE [QI HI])
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(define_mode_iterator I24MODE [HI SI])
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(define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
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(define_mode_attr modesuffix [(SI "") (DI "x")])
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(define_expand "memory_barrier"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
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"TARGET_V8 || TARGET_V9"
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*stbar"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
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"TARGET_V8"
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"stbar"
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[(set_attr "type" "multi")])
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;; membar #StoreStore | #LoadStore | #StoreLoad | #LoadLoad
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(define_insn "*membar"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
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"TARGET_V9"
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"membar\t15"
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[(set_attr "type" "multi")])
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(define_expand "sync_compare_and_swap<mode>"
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[(match_operand:I12MODE 0 "register_operand" "")
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(match_operand:I12MODE 1 "memory_operand" "")
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(match_operand:I12MODE 2 "register_operand" "")
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(match_operand:I12MODE 3 "register_operand" "")]
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"TARGET_V9"
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{
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sparc_expand_compare_and_swap_12 (operands[0], operands[1],
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operands[2], operands[3]);
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DONE;
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})
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(define_expand "sync_compare_and_swap<mode>"
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[(parallel
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(match_operand:I48MODE 1 "memory_operand" ""))
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(set (match_dup 1)
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(unspec_volatile:I48MODE
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[(match_operand:I48MODE 2 "register_operand" "")
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(match_operand:I48MODE 3 "register_operand" "")]
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UNSPECV_CAS))])]
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"TARGET_V9"
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{
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if (! REG_P (XEXP (operands[1], 0)))
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{
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rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
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operands[1] = replace_equiv_address (operands[1], addr);
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}
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emit_insn (gen_memory_barrier ());
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})
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(define_insn "*sync_compare_and_swap<mode>"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(match_operand:I48MODE 1 "memory_reg_operand" "+m"))
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(set (match_dup 1)
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(unspec_volatile:I48MODE
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[(match_operand:I48MODE 2 "register_operand" "r")
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(match_operand:I48MODE 3 "register_operand" "0")]
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UNSPECV_CAS))]
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"TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
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"cas<modesuffix>\t%1, %2, %0"
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[(set_attr "type" "multi")])
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(define_insn "*sync_compare_and_swapdi_v8plus"
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[(set (match_operand:DI 0 "register_operand" "=h")
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(match_operand:DI 1 "memory_reg_operand" "+m"))
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(set (match_dup 1)
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(unspec_volatile:DI
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[(match_operand:DI 2 "register_operand" "h")
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(match_operand:DI 3 "register_operand" "0")]
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UNSPECV_CAS))]
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"TARGET_V8PLUS"
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{
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if (sparc_check_64 (operands[3], insn) <= 0)
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output_asm_insn ("srl\t%L3, 0, %L3", operands);
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output_asm_insn ("sllx\t%H3, 32, %H3", operands);
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output_asm_insn ("or\t%L3, %H3, %L3", operands);
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if (sparc_check_64 (operands[2], insn) <= 0)
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output_asm_insn ("srl\t%L2, 0, %L2", operands);
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output_asm_insn ("sllx\t%H2, 32, %H3", operands);
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output_asm_insn ("or\t%L2, %H3, %H3", operands);
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output_asm_insn ("casx\t%1, %H3, %L3", operands);
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return "srlx\t%L3, 32, %H3";
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}
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[(set_attr "type" "multi")
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(set_attr "length" "8")])
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(define_expand "sync_lock_test_and_set<mode>"
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[(match_operand:I12MODE 0 "register_operand" "")
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(match_operand:I12MODE 1 "memory_operand" "")
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(match_operand:I12MODE 2 "arith_operand" "")]
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"!TARGET_V9"
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{
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if (operands[2] != const1_rtx)
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FAIL;
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if (TARGET_V8)
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emit_insn (gen_memory_barrier ());
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if (<MODE>mode != QImode)
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operands[1] = adjust_address (operands[1], QImode, 0);
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emit_insn (gen_ldstub<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_expand "sync_lock_test_and_setsi"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "")
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(unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "")]
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UNSPECV_SWAP))
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(set (match_dup 1)
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(match_operand:SI 2 "arith_operand" ""))])]
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""
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{
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if (! TARGET_V8 && ! TARGET_V9)
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{
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if (operands[2] != const1_rtx)
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FAIL;
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operands[1] = adjust_address (operands[1], QImode, 0);
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emit_insn (gen_ldstubsi (operands[0], operands[1]));
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DONE;
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}
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emit_insn (gen_memory_barrier ());
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operands[2] = force_reg (SImode, operands[2]);
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})
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(define_insn "*swapsi"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
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UNSPECV_SWAP))
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(set (match_dup 1)
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(match_operand:SI 2 "register_operand" "0"))]
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"TARGET_V8 || TARGET_V9"
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"swap\t%1, %0"
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[(set_attr "type" "multi")])
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(define_expand "ldstubqi"
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[(parallel [(set (match_operand:QI 0 "register_operand" "")
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(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")]
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UNSPECV_LDSTUB))
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(set (match_dup 1) (const_int -1))])]
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""
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"")
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(define_expand "ldstub<mode>"
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[(parallel [(set (match_operand:I24MODE 0 "register_operand" "")
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(zero_extend:I24MODE
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(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")]
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UNSPECV_LDSTUB)))
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(set (match_dup 1) (const_int -1))])]
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""
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"")
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(define_insn "*ldstubqi"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
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UNSPECV_LDSTUB))
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(set (match_dup 1) (const_int -1))]
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""
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"ldstub\t%1, %0"
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[(set_attr "type" "multi")])
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(define_insn "*ldstub<mode>"
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[(set (match_operand:I24MODE 0 "register_operand" "=r")
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(zero_extend:I24MODE
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(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
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UNSPECV_LDSTUB)))
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(set (match_dup 1) (const_int -1))]
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""
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"ldstub\t%1, %0"
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[(set_attr "type" "multi")])
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