482 lines
16 KiB
Markdown
482 lines
16 KiB
Markdown
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;; Predicate definitions for SPARC.
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;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Predicates for numerical constants.
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;; Return true if OP is the zero constant for MODE.
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(define_predicate "const_zero_operand"
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(and (match_code "const_int,const_double,const_vector")
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(match_test "op == CONST0_RTX (mode)")))
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;; Return true if OP is the one constant for MODE.
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(define_predicate "const_one_operand"
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(and (match_code "const_int,const_double,const_vector")
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(match_test "op == CONST1_RTX (mode)")))
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;; Return true if OP is the integer constant 4096.
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(define_predicate "const_4096_operand"
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(and (match_code "const_int")
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(match_test "INTVAL (op) == 4096")))
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;; Return true if OP is a constant that is representable by a 13-bit
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;; signed field. This is an acceptable immediate operand for most
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;; 3-address instructions.
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(define_predicate "small_int_operand"
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(and (match_code "const_int")
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(match_test "SPARC_SIMM13_P (INTVAL (op))")))
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;; Return true if OP is a constant operand for the umul instruction. That
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;; instruction sign-extends immediate values just like all other SPARC
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;; instructions, but interprets the extended result as an unsigned number.
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(define_predicate "uns_small_int_operand"
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(match_code "const_int,const_double")
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{
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#if HOST_BITS_PER_WIDE_INT == 32
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return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
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|| (GET_CODE (op) == CONST_DOUBLE
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&& CONST_DOUBLE_HIGH (op) == 0
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&& (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
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#else
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return (GET_CODE (op) == CONST_INT
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&& ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
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|| (INTVAL (op) >= 0xFFFFF000
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&& INTVAL (op) <= 0xFFFFFFFF)));
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#endif
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})
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;; Return true if OP is a constant that can be loaded by the sethi instruction.
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;; The first test avoids emitting sethi to load zero for example.
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(define_predicate "const_high_operand"
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(and (match_code "const_int")
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(and (not (match_operand 0 "small_int_operand"))
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(match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))"))))
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;; Return true if OP is a constant whose 1's complement can be loaded by the
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;; sethi instruction.
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(define_predicate "const_compl_high_operand"
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(and (match_code "const_int")
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(and (not (match_operand 0 "small_int_operand"))
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(match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))"))))
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;; Return true if OP is a FP constant that needs to be loaded by the sethi/losum
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;; pair of instructions.
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(define_predicate "fp_const_high_losum_operand"
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(match_operand 0 "const_double_operand")
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{
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gcc_assert (mode == SFmode);
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return fp_high_losum_p (op);
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})
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;; Return true if OP is a const_double or const_vector.
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(define_predicate "const_double_or_vector_operand"
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(match_code "const_double,const_vector"))
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;; Predicates for symbolic constants.
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;; Return true if OP is either a symbol reference or a sum of a symbol
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;; reference and a constant.
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(define_predicate "symbolic_operand"
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(match_code "symbol_ref,label_ref,const")
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{
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enum machine_mode omode = GET_MODE (op);
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if (omode != mode && omode != VOIDmode && mode != VOIDmode)
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return false;
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switch (GET_CODE (op))
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{
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case SYMBOL_REF:
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return !SYMBOL_REF_TLS_MODEL (op);
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case LABEL_REF:
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return true;
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case CONST:
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op = XEXP (op, 0);
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return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
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&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
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|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
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&& GET_CODE (XEXP (op, 1)) == CONST_INT);
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default:
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gcc_unreachable ();
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}
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})
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;; Return true if OP is a symbolic operand for the TLS Global Dynamic model.
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(define_predicate "tgd_symbolic_operand"
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(and (match_code "symbol_ref")
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(match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_GLOBAL_DYNAMIC")))
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;; Return true if OP is a symbolic operand for the TLS Local Dynamic model.
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(define_predicate "tld_symbolic_operand"
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(and (match_code "symbol_ref")
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(match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_DYNAMIC")))
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;; Return true if OP is a symbolic operand for the TLS Initial Exec model.
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(define_predicate "tie_symbolic_operand"
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(and (match_code "symbol_ref")
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(match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC")))
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;; Return true if OP is a symbolic operand for the TLS Local Exec model.
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(define_predicate "tle_symbolic_operand"
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(and (match_code "symbol_ref")
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(match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC")))
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;; Return true if the operand is an argument used in generating PIC references
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;; in either the medium/low or embedded medium/anywhere code models on V9.
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;; Check for (const (minus (symbol_ref:GOT)
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;; (const (minus (label) (pc)))))
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(define_predicate "medium_pic_operand"
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(match_code "const")
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{
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/* Check for (const (minus (symbol_ref:GOT)
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(const (minus (label) (pc))))). */
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op = XEXP (op, 0);
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return GET_CODE (op) == MINUS
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&& GET_CODE (XEXP (op, 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (op, 1)) == CONST
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&& GET_CODE (XEXP (XEXP (op, 1), 0)) == MINUS;
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})
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;; Return true if OP is a LABEL_REF of mode MODE.
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(define_predicate "label_ref_operand"
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(and (match_code "label_ref")
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(match_test "GET_MODE (op) == mode")))
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;; Return true if OP is a data segment reference. This includes the readonly
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;; data segment or, in other words, anything but the text segment.
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;; This is needed in the embedded medium/anywhere code model on V9. These
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;; values are accessed with EMBMEDANY_BASE_REG. */
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(define_predicate "data_segment_operand"
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(match_code "symbol_ref,plus,const")
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{
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switch (GET_CODE (op))
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{
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case SYMBOL_REF :
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return ! SYMBOL_REF_FUNCTION_P (op);
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case PLUS :
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/* Assume canonical format of symbol + constant.
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Fall through. */
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case CONST :
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return data_segment_operand (XEXP (op, 0), VOIDmode);
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default :
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gcc_unreachable ();
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}
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})
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;; Return true if OP is a text segment reference.
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;; This is needed in the embedded medium/anywhere code model on V9.
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(define_predicate "text_segment_operand"
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(match_code "label_ref,symbol_ref,plus,const")
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{
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switch (GET_CODE (op))
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{
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case LABEL_REF :
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return true;
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case SYMBOL_REF :
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return SYMBOL_REF_FUNCTION_P (op);
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case PLUS :
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/* Assume canonical format of symbol + constant.
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Fall through. */
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case CONST :
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return text_segment_operand (XEXP (op, 0), VOIDmode);
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default :
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gcc_unreachable ();
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}
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})
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;; Predicates for registers.
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;; Return true if OP is either the zero constant or a register.
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(define_predicate "register_or_zero_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "const_zero_operand")))
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;; Return true if OP is a register operand in a floating point register.
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(define_predicate "fp_register_operand"
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(match_operand 0 "register_operand")
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{
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op); /* Possibly a MEM */
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return REG_P (op) && SPARC_FP_REG_P (REGNO (op));
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})
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;; Return true if OP is an integer register.
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(define_special_predicate "int_register_operand"
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(ior (match_test "register_operand (op, SImode)")
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(match_test "TARGET_ARCH64 && register_operand (op, DImode)")))
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;; Return true if OP is a floating point condition code register.
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(define_predicate "fcc_register_operand"
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(match_code "reg")
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{
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if (mode != VOIDmode && mode != GET_MODE (op))
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return false;
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if (mode == VOIDmode
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&& (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
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return false;
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#if 0 /* ??? 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
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if (reg_renumber == 0)
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return REGNO (op) >= FIRST_PSEUDO_REGISTER;
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return REGNO_OK_FOR_CCFP_P (REGNO (op));
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#else
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return ((unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG) < 4;
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#endif
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})
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;; Return true if OP is the floating point condition code register fcc0.
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(define_predicate "fcc0_register_operand"
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(match_code "reg")
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{
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if (mode != VOIDmode && mode != GET_MODE (op))
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return false;
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if (mode == VOIDmode
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&& (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
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return false;
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return REGNO (op) == SPARC_FCC_REG;
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})
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;; Return true if OP is an integer or floating point condition code register.
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(define_predicate "icc_or_fcc_register_operand"
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(match_code "reg")
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{
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if (REGNO (op) == SPARC_ICC_REG)
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{
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if (mode != VOIDmode && mode != GET_MODE (op))
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return false;
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if (mode == VOIDmode
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&& GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
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return false;
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return true;
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}
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return fcc_register_operand (op, mode);
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})
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;; Predicates for arithmetic instructions.
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;; Return true if OP is a register, or is a constant that is representable
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;; by a 13-bit signed field. This is an acceptable operand for most
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;; 3-address instructions.
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(define_predicate "arith_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "small_int_operand")))
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;; 64-bit: Same as above.
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;; 32-bit: Return true if OP is a register, or is a constant that is
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;; representable by a couple of 13-bit signed fields. This is an
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;; acceptable operand for most 3-address splitters.
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(define_predicate "arith_double_operand"
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(match_code "const_int,const_double,reg,subreg")
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{
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bool arith_simple_operand = arith_operand (op, mode);
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HOST_WIDE_INT m1, m2;
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if (TARGET_ARCH64 || arith_simple_operand)
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return arith_simple_operand;
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#if HOST_BITS_PER_WIDE_INT == 32
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if (GET_CODE (op) != CONST_DOUBLE)
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return false;
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m1 = CONST_DOUBLE_LOW (op);
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m2 = CONST_DOUBLE_HIGH (op);
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#else
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if (GET_CODE (op) != CONST_INT)
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return false;
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m1 = trunc_int_for_mode (INTVAL (op), SImode);
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m2 = trunc_int_for_mode (INTVAL (op) >> 32, SImode);
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#endif
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return SPARC_SIMM13_P (m1) && SPARC_SIMM13_P (m2);
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})
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;; Return true if OP is suitable as second operand for add/sub.
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(define_predicate "arith_add_operand"
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(ior (match_operand 0 "arith_operand")
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(match_operand 0 "const_4096_operand")))
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;; Return true if OP is suitable as second double operand for add/sub.
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(define_predicate "arith_double_add_operand"
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(match_code "const_int,const_double,reg,subreg")
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{
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bool _arith_double_operand = arith_double_operand (op, mode);
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if (_arith_double_operand)
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return true;
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return TARGET_ARCH64 && const_4096_operand (op, mode);
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})
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;; Return true if OP is a register, or is a CONST_INT that can fit in a
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;; signed 10-bit immediate field. This is an acceptable SImode operand for
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;; the movrcc instructions.
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(define_predicate "arith10_operand"
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(ior (match_operand 0 "register_operand")
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(and (match_code "const_int")
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(match_test "SPARC_SIMM10_P (INTVAL (op))"))))
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;; Return true if OP is a register, or is a CONST_INT that can fit in a
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;; signed 11-bit immediate field. This is an acceptable SImode operand for
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;; the movcc instructions.
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(define_predicate "arith11_operand"
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(ior (match_operand 0 "register_operand")
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|
(and (match_code "const_int")
|
||
|
|
(match_test "SPARC_SIMM11_P (INTVAL (op))"))))
|
||
|
|
|
||
|
|
;; Return true if OP is a register or a constant for the umul instruction.
|
||
|
|
(define_predicate "uns_arith_operand"
|
||
|
|
(ior (match_operand 0 "register_operand")
|
||
|
|
(match_operand 0 "uns_small_int_operand")))
|
||
|
|
|
||
|
|
|
||
|
|
;; Predicates for miscellaneous instructions.
|
||
|
|
|
||
|
|
;; Return true if OP is valid for the lhs of a comparison insn.
|
||
|
|
(define_predicate "compare_operand"
|
||
|
|
(match_code "reg,subreg,zero_extract")
|
||
|
|
{
|
||
|
|
if (GET_CODE (op) == ZERO_EXTRACT)
|
||
|
|
return (register_operand (XEXP (op, 0), mode)
|
||
|
|
&& small_int_operand (XEXP (op, 1), mode)
|
||
|
|
&& small_int_operand (XEXP (op, 2), mode)
|
||
|
|
/* This matches cmp_zero_extract. */
|
||
|
|
&& ((mode == SImode
|
||
|
|
&& INTVAL (XEXP (op, 2)) > 19)
|
||
|
|
/* This matches cmp_zero_extract_sp64. */
|
||
|
|
|| (TARGET_ARCH64
|
||
|
|
&& mode == DImode
|
||
|
|
&& INTVAL (XEXP (op, 2)) > 51)));
|
||
|
|
else
|
||
|
|
return register_operand (op, mode);
|
||
|
|
})
|
||
|
|
|
||
|
|
;; Return true if OP is a valid operand for the source of a move insn.
|
||
|
|
(define_predicate "input_operand"
|
||
|
|
(match_code "const_int,const_double,const_vector,reg,subreg,mem")
|
||
|
|
{
|
||
|
|
enum mode_class mclass;
|
||
|
|
|
||
|
|
/* If both modes are non-void they must be the same. */
|
||
|
|
if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
mclass = GET_MODE_CLASS (mode);
|
||
|
|
|
||
|
|
/* Allow any 1-instruction integer constant. */
|
||
|
|
if (mclass == MODE_INT
|
||
|
|
&& (small_int_operand (op, mode) || const_high_operand (op, mode)))
|
||
|
|
return true;
|
||
|
|
|
||
|
|
/* If 32-bit mode and this is a DImode constant, allow it
|
||
|
|
so that the splits can be generated. */
|
||
|
|
if (TARGET_ARCH32
|
||
|
|
&& mode == DImode
|
||
|
|
&& (GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT))
|
||
|
|
return true;
|
||
|
|
|
||
|
|
if ((mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE)
|
||
|
|
|| (mclass == MODE_VECTOR_INT && GET_CODE (op) == CONST_VECTOR))
|
||
|
|
return true;
|
||
|
|
|
||
|
|
if (register_operand (op, mode))
|
||
|
|
return true;
|
||
|
|
|
||
|
|
/* If this is a SUBREG, look inside so that we handle paradoxical ones. */
|
||
|
|
if (GET_CODE (op) == SUBREG)
|
||
|
|
op = SUBREG_REG (op);
|
||
|
|
|
||
|
|
/* Check for valid MEM forms. */
|
||
|
|
if (GET_CODE (op) == MEM)
|
||
|
|
return memory_address_p (mode, XEXP (op, 0));
|
||
|
|
|
||
|
|
return false;
|
||
|
|
})
|
||
|
|
|
||
|
|
;; Return true if OP is an address suitable for a call insn.
|
||
|
|
;; Call insn on SPARC can take a PC-relative constant address
|
||
|
|
;; or any regular memory address.
|
||
|
|
(define_predicate "call_address_operand"
|
||
|
|
(ior (match_operand 0 "symbolic_operand")
|
||
|
|
(match_test "memory_address_p (Pmode, op)")))
|
||
|
|
|
||
|
|
;; Return true if OP is an operand suitable for a call insn.
|
||
|
|
(define_predicate "call_operand"
|
||
|
|
(and (match_code "mem")
|
||
|
|
(match_test "call_address_operand (XEXP (op, 0), mode)")))
|
||
|
|
|
||
|
|
|
||
|
|
;; Predicates for operators.
|
||
|
|
|
||
|
|
;; Return true if OP is a comparison operator. This allows the use of
|
||
|
|
;; MATCH_OPERATOR to recognize all the branch insns.
|
||
|
|
(define_predicate "noov_compare_operator"
|
||
|
|
(match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu")
|
||
|
|
{
|
||
|
|
enum rtx_code code = GET_CODE (op);
|
||
|
|
if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
|
||
|
|
|| GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
|
||
|
|
/* These are the only branches which work with CC_NOOVmode. */
|
||
|
|
return (code == EQ || code == NE || code == GE || code == LT);
|
||
|
|
return true;
|
||
|
|
})
|
||
|
|
|
||
|
|
;; Return true if OP is a 64-bit comparison operator. This allows the use of
|
||
|
|
;; MATCH_OPERATOR to recognize all the branch insns.
|
||
|
|
(define_predicate "noov_compare64_operator"
|
||
|
|
(and (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu")
|
||
|
|
(match_test "TARGET_V9"))
|
||
|
|
{
|
||
|
|
enum rtx_code code = GET_CODE (op);
|
||
|
|
if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
|
||
|
|
/* These are the only branches which work with CCX_NOOVmode. */
|
||
|
|
return (code == EQ || code == NE || code == GE || code == LT);
|
||
|
|
return (GET_MODE (XEXP (op, 0)) == CCXmode);
|
||
|
|
})
|
||
|
|
|
||
|
|
;; Return true if OP is a comparison operator suitable for use in V9
|
||
|
|
;; conditional move or branch on register contents instructions.
|
||
|
|
(define_predicate "v9_register_compare_operator"
|
||
|
|
(match_code "eq,ne,ge,lt,le,gt"))
|
||
|
|
|
||
|
|
;; Return true if OP is an operator which can set the condition codes
|
||
|
|
;; explicitly. We do not include PLUS and MINUS because these
|
||
|
|
;; require CC_NOOVmode, which we handle explicitly.
|
||
|
|
(define_predicate "cc_arith_operator"
|
||
|
|
(match_code "and,ior,xor"))
|
||
|
|
|
||
|
|
;; Return true if OP is an operator which can bitwise complement its
|
||
|
|
;; second operand and set the condition codes explicitly.
|
||
|
|
;; XOR is not here because combine canonicalizes (xor (not ...) ...)
|
||
|
|
;; and (xor ... (not ...)) to (not (xor ...)). */
|
||
|
|
(define_predicate "cc_arith_not_operator"
|
||
|
|
(match_code "and,ior"))
|
||
|
|
|
||
|
|
;; Return true if OP is memory operand with just [%reg] addressing mode.
|
||
|
|
(define_predicate "memory_reg_operand"
|
||
|
|
(and (match_code "mem")
|
||
|
|
(and (match_operand 0 "memory_operand")
|
||
|
|
(match_test "REG_P (XEXP (op, 0))"))))
|