401 lines
13 KiB
Markdown
401 lines
13 KiB
Markdown
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;; Scheduling description for cell processor.
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;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009
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;; Free Software Foundation, Inc.
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;; Contributed by Sony Computer Entertainment, Inc.,
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;; This file is free software; you can redistribute it and/or modify it under
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;; the terms of the GNU General Public License as published by the Free
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;; Software Foundation; either version 3 of the License, or (at your option)
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;; any later version.
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;; This file is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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;; for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Sources: BE BOOK4 (/sfs/enc/doc/PPU_BookIV_DD3.0_latest.pdf)
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;; BE Architecture *DD3.0 and DD3.1*
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;; This file simulate PPU processor unit backend of pipeline, maualP24.
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;; manual P27, stall and flush points
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;; IU, XU, VSU, dispatcher decodes and dispatch 2 insns per cycle in program
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;; order, the grouped address are aligned by 8
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;; This file only simulate one thread situation
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;; XU executes all fixed point insns(3 units, a simple alu, a complex unit,
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;; and load/store unit)
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;; VSU executes all scalar floating points insn(a float unit),
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;; VMX insns(VMX unit, 4 sub units, simple, permute, complex, floating point)
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;; Dual issue combination
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;; FXU LSU BR VMX VMX
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;; (sx,cx,vsu_fp,fp_arith) (perm,vsu_ls,fp_ls)
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;;FXU X
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;;LSU X X X
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;;BR X
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;;VMX(sx,cx,vsu_fp,fp_arth) X
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;;VMX(perm,vsu_ls, fp_ls) X
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;; X are illegal combination.
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;; Dual issue exceptions:
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;;(1) nop-pipelined FXU instr in slot 0
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;;(2) non-pipelined FPU inst in slot 0
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;; CSI instr(contex-synchronizing insn)
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;; Microcode insn
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;; BRU unit: bru(none register stall), bru_cr(cr register stall)
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;; VSU unit: vus(vmx simple), vup(vmx permute), vuc(vmx complex),
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;; vuf(vmx float), fpu(floats). fpu_div is hypothetical, it is for
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;; nonpipelined simulation
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;; micr insns will stall at least 7 cycles to get the first instr from ROM,
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;; micro instructions are not dual issued.
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;; slot0 is older than slot1
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;; non-pipelined insn need to be in slot1 to avoid 1cycle stall
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;; There different stall point
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;; IB2, only stall one thread if stall here, so try to stall here as much as
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;; we can
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;; condition(1) insert nop, OR and ORI instruction form
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;; condition(2) flush happens, in case of: RAW, WAW, D-ERAT miss, or
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;; CR0-access while stdcx, or stwcx
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;; IS2 stall ;; Page91 for details
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;; VQ8 stall
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;; IS2 stall can be activated by VQ8 stall and trying to issue a vsu instr to
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;; the vsu issue queue
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;;(define_automaton "cellxu")
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;;(define_cpu_unit "fxu_cell,lsu_cell,bru_cell,vsu1_cell,vsu2_cell" "cellxu")
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;; ndfa
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(define_automaton "cellxu,cellvsu,cellbru,cell_mis")
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(define_cpu_unit "fxu_cell,lsu_cell" "cellxu")
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(define_cpu_unit "bru_cell" "cellbru")
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(define_cpu_unit "vsu1_cell,vsu2_cell" "cellvsu")
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(define_cpu_unit "slot0,slot1" "cell_mis")
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(absence_set "slot0" "slot1")
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(define_reservation "nonpipeline" "fxu_cell+lsu_cell+vsu1_cell+vsu2_cell")
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(define_reservation "slot01" "slot0|slot1")
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;; Load/store
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;; lmw, lswi, lswx are only generated for optimize for space, MC,
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;; these instr are not simulated
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(define_insn_reservation "cell-load" 2
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "cell"))
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"slot01,lsu_cell")
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;; ldux, ldu, lbzux, lbzu, hardware breaks it down to two instrs,
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;; if with 32bytes alignment, CMC
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(define_insn_reservation "cell-load-ux" 2
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(and (eq_attr "type" "load_ux,load_u")
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(eq_attr "cpu" "cell"))
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"slot01,fxu_cell+lsu_cell")
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;; lha, lhax, lhau, lhaux, lwa, lwax, lwaux, MC, latency unknown
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;; 11/7, 11/8, 11/12
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(define_insn_reservation "cell-load-ext" 2
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(and (eq_attr "type" "load_ext,load_ext_u,load_ext_ux")
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(eq_attr "cpu" "cell"))
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"slot01,fxu_cell+lsu_cell")
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;;lfs,lfsx,lfd,lfdx, 1 cycle
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(define_insn_reservation "cell-fpload" 1
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "cell"))
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"vsu2_cell+lsu_cell+slot01")
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;; lfsu,lfsux,lfdu,lfdux 1cycle(fpr) 2 cycle(gpr)
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(define_insn_reservation "cell-fpload-update" 1
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(and (eq_attr "type" "fpload,fpload_u,fpload_ux")
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(eq_attr "cpu" "cell"))
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"fxu_cell+vsu2_cell+lsu_cell+slot01")
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(define_insn_reservation "cell-vecload" 2
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(and (eq_attr "type" "vecload")
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(eq_attr "cpu" "cell"))
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"slot01,vsu2_cell+lsu_cell")
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;;st? stw(MC)
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(define_insn_reservation "cell-store" 1
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(and (eq_attr "type" "store")
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(eq_attr "cpu" "cell"))
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"lsu_cell+slot01")
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;;stdux, stdu, (hardware breaks into store and add) 2 for update reg
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(define_insn_reservation "cell-store-update" 1
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(and (eq_attr "type" "store_ux,store_u")
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(eq_attr "cpu" "cell"))
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"fxu_cell+lsu_cell+slot01")
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(define_insn_reservation "cell-fpstore" 1
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(and (eq_attr "type" "fpstore")
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(eq_attr "cpu" "cell"))
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"vsu2_cell+lsu_cell+slot01")
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(define_insn_reservation "cell-fpstore-update" 1
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(and (eq_attr "type" "fpstore_ux,fpstore_u")
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(eq_attr "cpu" "cell"))
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"vsu2_cell+fxu_cell+lsu_cell+slot01")
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(define_insn_reservation "cell-vecstore" 1
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(and (eq_attr "type" "vecstore")
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(eq_attr "cpu" "cell"))
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"vsu2_cell+lsu_cell+slot01")
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;; Integer latency is 2 cycles
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(define_insn_reservation "cell-integer" 2
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(and (eq_attr "type" "integer,insert_dword,shift,trap,\
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var_shift_rotate,cntlz,exts,isel")
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(eq_attr "cpu" "cell"))
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"slot01,fxu_cell")
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;; Two integer latency is 4 cycles
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(define_insn_reservation "cell-two" 4
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "cell"))
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"slot01,fxu_cell,fxu_cell*2")
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;; Three integer latency is 6 cycles
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(define_insn_reservation "cell-three" 6
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "cell"))
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"slot01,fxu_cell,fxu_cell*4")
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;; rlwimi, alter cr0
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(define_insn_reservation "cell-insert" 2
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(and (eq_attr "type" "insert_word")
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(eq_attr "cpu" "cell"))
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"slot01,fxu_cell")
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;; cmpi, cmpli, cmpla, add, addo, sub, subo, alter cr0
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(define_insn_reservation "cell-cmp" 1
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(and (eq_attr "type" "cmp")
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(eq_attr "cpu" "cell"))
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"fxu_cell+slot01")
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;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
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(define_insn_reservation "cell-fast-cmp" 2
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(and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
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var_delayed_compare")
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(eq_attr "cpu" "cell"))
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(eq_attr "cell_micro" "not"))
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"slot01,fxu_cell")
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(define_insn_reservation "cell-cmp-microcoded" 9
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(and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
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var_delayed_compare")
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(eq_attr "cpu" "cell"))
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(eq_attr "cell_micro" "always"))
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"slot0+slot1,fxu_cell,fxu_cell*7")
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;; mulld
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(define_insn_reservation "cell-lmul" 15
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(and (eq_attr "type" "lmul")
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(eq_attr "cpu" "cell"))
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"slot1,nonpipeline,nonpipeline*13")
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;; mulld. is microcoded
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(define_insn_reservation "cell-lmul-cmp" 22
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(and (eq_attr "type" "lmul_compare")
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(eq_attr "cpu" "cell"))
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"slot0+slot1,nonpipeline,nonpipeline*20")
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;; mulli, 6 cycles
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(define_insn_reservation "cell-imul23" 6
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(and (eq_attr "type" "imul2,imul3")
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(eq_attr "cpu" "cell"))
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"slot1,nonpipeline,nonpipeline*4")
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;; mullw, 9
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(define_insn_reservation "cell-imul" 9
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(and (eq_attr "type" "imul")
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(eq_attr "cpu" "cell"))
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"slot1,nonpipeline,nonpipeline*7")
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;; divide
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(define_insn_reservation "cell-idiv" 32
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "cell"))
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"slot1,nonpipeline,nonpipeline*30")
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(define_insn_reservation "cell-ldiv" 64
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(and (eq_attr "type" "ldiv")
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(eq_attr "cpu" "cell"))
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"slot1,nonpipeline,nonpipeline*62")
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;;mflr and mfctr are pipelined
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(define_insn_reservation "cell-mfjmpr" 1
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "cell"))
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"slot01+bru_cell")
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;;mtlr and mtctr,
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;;mtspr fully pipelined
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(define_insn_reservation "cell-mtjmpr" 1
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "cell"))
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"bru_cell+slot01")
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;; Branches
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;; b, ba, bl, bla, unconditional branch always predicts correctly n/a latency
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;; bcctr, bcctrl, latency 2, actually adjust by be to 4
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(define_insn_reservation "cell-branch" 1
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(and (eq_attr "type" "branch")
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(eq_attr "cpu" "cell"))
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"bru_cell+slot1")
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(define_insn_reservation "cell-branchreg" 1
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(and (eq_attr "type" "jmpreg")
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(eq_attr "cpu" "cell"))
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"bru_cell+slot1")
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;; cr hazard
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;; page 90, special cases for CR hazard, only one instr can access cr per cycle
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;; if insn reads CR following a stwcx, pipeline stall till stwcx finish
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(define_insn_reservation "cell-crlogical" 1
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "cell"))
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"bru_cell+slot01")
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;; mfcrf and mfcr is about 34 cycles and nonpipelined
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(define_insn_reservation "cell-mfcr" 34
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(and (eq_attr "type" "mfcrf,mfcr")
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(eq_attr "cpu" "cell"))
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"slot1,nonpipeline,nonpipeline*32")
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;; mtcrf (1 field)
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(define_insn_reservation "cell-mtcrf" 1
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "cell"))
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"fxu_cell+slot01")
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; Basic FP latency is 10 cycles, thoughput is 1/cycle
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(define_insn_reservation "cell-fp" 10
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(and (eq_attr "type" "fp,dmul")
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(eq_attr "cpu" "cell"))
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"slot01,vsu1_cell,vsu1_cell*8")
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(define_insn_reservation "cell-fpcompare" 1
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "cell"))
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"vsu1_cell+slot01")
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;; sdiv thoughput 1/74, not pipelined but only in the FPU
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(define_insn_reservation "cell-sdiv" 74
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(and (eq_attr "type" "sdiv,ddiv")
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(eq_attr "cpu" "cell"))
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"slot1,nonpipeline,nonpipeline*72")
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;; fsqrt thoughput 1/84, not pipelined but only in the FPU
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(define_insn_reservation "cell-sqrt" 84
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(and (eq_attr "type" "ssqrt,dsqrt")
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(eq_attr "cpu" "cell"))
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"slot1,nonpipeline,nonpipeline*82")
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; VMX
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(define_insn_reservation "cell-vecsimple" 4
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(and (eq_attr "type" "vecsimple")
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(eq_attr "cpu" "cell"))
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"slot01,vsu1_cell,vsu1_cell*2")
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;; mult, div, madd
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(define_insn_reservation "cell-veccomplex" 10
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(and (eq_attr "type" "veccomplex")
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(eq_attr "cpu" "cell"))
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"slot01,vsu1_cell,vsu1_cell*8")
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;; TODO: add support for recording instructions
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(define_insn_reservation "cell-veccmp" 4
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(and (eq_attr "type" "veccmp")
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(eq_attr "cpu" "cell"))
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"slot01,vsu1_cell,vsu1_cell*2")
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(define_insn_reservation "cell-vecfloat" 12
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(and (eq_attr "type" "vecfloat")
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(eq_attr "cpu" "cell"))
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"slot01,vsu1_cell,vsu1_cell*10")
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(define_insn_reservation "cell-vecperm" 4
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(and (eq_attr "type" "vecperm")
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||
|
|
(eq_attr "cpu" "cell"))
|
||
|
|
"slot01,vsu2_cell,vsu2_cell*2")
|
||
|
|
|
||
|
|
;; New for 4.2, syncs
|
||
|
|
|
||
|
|
(define_insn_reservation "cell-sync" 11
|
||
|
|
(and (eq_attr "type" "sync")
|
||
|
|
(eq_attr "cpu" "cell"))
|
||
|
|
"slot01,lsu_cell,lsu_cell*9")
|
||
|
|
|
||
|
|
(define_insn_reservation "cell-isync" 11
|
||
|
|
(and (eq_attr "type" "isync")
|
||
|
|
(eq_attr "cpu" "cell"))
|
||
|
|
"slot01,lsu_cell,lsu_cell*9")
|
||
|
|
|
||
|
|
(define_insn_reservation "cell-load_l" 11
|
||
|
|
(and (eq_attr "type" "load_l")
|
||
|
|
(eq_attr "cpu" "cell"))
|
||
|
|
"slot01,lsu_cell,lsu_cell*9")
|
||
|
|
|
||
|
|
(define_insn_reservation "cell-store_c" 11
|
||
|
|
(and (eq_attr "type" "store_c")
|
||
|
|
(eq_attr "cpu" "cell"))
|
||
|
|
"slot01,lsu_cell,lsu_cell*9")
|
||
|
|
|
||
|
|
;; RAW register dependency
|
||
|
|
|
||
|
|
;; addi r3, r3, 1
|
||
|
|
;; lw r4,offset(r3)
|
||
|
|
;; there are 5 cycle deplay for r3 bypassing
|
||
|
|
;; there are 5 cycle delay for a dependent load after a load
|
||
|
|
(define_bypass 5 "cell-integer" "cell-load")
|
||
|
|
(define_bypass 5 "cell-integer" "cell-load-ext")
|
||
|
|
(define_bypass 5 "cell-load,cell-load-ext" "cell-load,cell-load-ext")
|
||
|
|
|
||
|
|
;; there is a 6 cycle delay after a fp compare until you can use the cr.
|
||
|
|
(define_bypass 6 "cell-fpcompare" "cell-branch,cell-branchreg,cell-mfcr,cell-crlogical")
|
||
|
|
|
||
|
|
;; VXU float RAW
|
||
|
|
(define_bypass 11 "cell-vecfloat" "cell-vecfloat")
|
||
|
|
|
||
|
|
;; VXU and FPU
|
||
|
|
(define_bypass 6 "cell-veccomplex" "cell-vecsimple")
|
||
|
|
;;(define_bypass 6 "cell-veccompare" "cell-branch,cell-branchreg")
|
||
|
|
(define_bypass 3 "cell-vecfloat" "cell-veccomplex")
|
||
|
|
; this is not correct,
|
||
|
|
;; this is a stall in general and not dependent on result
|
||
|
|
(define_bypass 13 "cell-vecstore" "cell-fpstore")
|
||
|
|
; this is not correct, this can never be true, not dependent on result
|
||
|
|
(define_bypass 7 "cell-fp" "cell-fpload")
|
||
|
|
;; vsu1 should avoid writing to the same target register as vsu2 insn
|
||
|
|
;; within 12 cycles.
|
||
|
|
|
||
|
|
;; WAW hazard
|
||
|
|
|
||
|
|
;; the target of VSU estimate should not be reused within 10 dispatch groups
|
||
|
|
;; the target of VSU float should not be reused within 8 dispatch groups
|
||
|
|
;; the target of VSU complex should not be reused within 5 dispatch groups
|
||
|
|
;; FP LOAD should not reuse an FPU Arithmetic target with 6 dispatch gropus
|
||
|
|
|
||
|
|
;; mtctr-bcctr/bcctrl, branch target ctr register shadow update at
|
||
|
|
;; ex4 stage(10 cycles)
|
||
|
|
(define_bypass 10 "cell-mtjmpr" "cell-branchreg")
|
||
|
|
|
||
|
|
;;Things are not simulated:
|
||
|
|
;; update instruction, update address gpr are not simulated
|
||
|
|
;; vrefp, vrsqrtefp have latency(14), currently simulated as 12 cycle float
|
||
|
|
;; insns
|
||
|
|
|