338 lines
11 KiB
Markdown
338 lines
11 KiB
Markdown
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;; Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;
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;; .........................
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;;
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;; DFA-based pipeline description for Sandcraft SR3 (MIPS64 based)
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;;
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;; The SR3 is described as:
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;; - nine-stage pipeline, insn buffering with out-of-order issue to
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;; multiple function units, with an average dispatch rate of 2
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;; insn.s per cycle (max 6 insns: 2 fpu, 4 cpu).
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;;
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;; The details on this are scant except for a diagram in
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;; Chap. 6 of Rev. 1.0 SR3 Spec.
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;;
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;; The model employed below is designed to closely approximate the
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;; published latencies. Emulation of out-of-order issue and the insn
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;; buffering is done via a VLIW dispatch style (with a packing of 6 insns);
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;; the function unit reservations restrictions (define_*_set) are
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;; contrived to support published timings.
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;;
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;; Reference:
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;; "SR3 Microprocessor Specification, System development information,"
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;; Revision 1.0, 13 December 2000.
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;;
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;;
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;; Reservation model is based on:
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;; 1) Figure 6-1, from the 1.0 specification.
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;; 2) Chapter 19, from the 1.0 specification.
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;; 3) following questions(Red Hat)/answers(Sandcraft):
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;; RH> From Section 19.1
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;; RH> 1) In terms of figure 6-1, are all the instructions in
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;; RH> table 19-1 restricted
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;; RH> to ALUx? When ALUx is not in use for an instruction in table;; RH> 19-1 is
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;; RH> it fully compatible with all insns that issue to ALUy?
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;;
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;; Yes, all the instructions in Table 19-1 only go to ALUX, and all the
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;; instructions that can be issued to ALUY can also be issued to ALUX.
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;;
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;;
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;; RH> From Section 19.2
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;; RH> 2) Explain conditional moves execution path (in terms of
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;; RH> figure 6-1)
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;;
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;; Conditional move of integer registers (based on floating point condition
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;; codes or integer register value) go to ALUX or ALUY.
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;;
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;; RH> 3) Explain floating point store execution path (in terms of
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;; RH> figure 6-1)
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;;
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;; Floating point stores go to Ld/St and go to MOV in the floating point
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;; pipeline.
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;;
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;; Floating point loads go to Ld/St and go to LOAD in the floating point
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;; pipeline.
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;;
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;; RH> 4) Explain branch on floating condition (in terms of figure 6-1);;
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;; Branch on floating condition go to BRU.
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;;
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;; RH> 5) Is the column for single RECIP instruction latency correct?
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;; RH> What about for RSQRT single and double?
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;;
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;; The latency/repeat for RECIP and RSQRT are correct.
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;;
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;;
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;; Use four automata to isolate long latency operations, and to
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;; reduce the complexity of cpu+fpu, reducing space.
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;;
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(define_automaton "sr71_cpu, sr71_cpu1, sr71_cp1, sr71_cp2, sr71_fextra, sr71_imacc")
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;; feeders for CPU function units and feeders for fpu (CP1 interface)
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(define_cpu_unit "sr_iss0,sr_iss1,sr_iss2,sr_iss3,sr_iss4,sr_iss5" "sr71_cpu")
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;; CPU function units
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(define_cpu_unit "ipu_bru" "sr71_cpu1")
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(define_cpu_unit "ipu_alux" "sr71_cpu1")
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(define_cpu_unit "ipu_aluy" "sr71_cpu1")
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(define_cpu_unit "ipu_ldst" "sr71_cpu1")
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(define_cpu_unit "ipu_macc_iter" "sr71_imacc")
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;; Floating-point unit (Co-processor interface 1).
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(define_cpu_unit "fpu_mov" "sr71_cp1")
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(define_cpu_unit "fpu_load" "sr71_cp1")
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(define_cpu_unit "fpu_fpu" "sr71_cp2")
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;; fictitous unit to track long float insns with separate automaton
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(define_cpu_unit "fpu_iter" "sr71_fextra")
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;;
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;; Define common execution path (reservation) combinations
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;;
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;;
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(define_reservation "cpu_iss" "sr_iss0|sr_iss1|sr_iss2|sr_iss3")
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;; two cycles are used for instruction using the fpu as it runs
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;; at half the clock speed of the cpu. By adding an extra cycle
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;; to the issue units, the default/minimum "repeat" dispatch delay is
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;; accounted for all insn.s
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(define_reservation "cp1_iss" "(sr_iss4*2)|(sr_iss5*2)")
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(define_reservation "serial_dispatch" "sr_iss0+sr_iss1+sr_iss2+sr_iss3+sr_iss4+sr_iss5")
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;; Simulate a 6 insn VLIW dispatch, 1 cycle in dispatch followed by
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;; reservation of function unit.
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(define_reservation "ri_insns" "cpu_iss,(ipu_alux|ipu_aluy)")
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(define_reservation "ri_mem" "cpu_iss,ipu_ldst")
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(define_reservation "ri_alux" "cpu_iss,ipu_alux")
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(define_reservation "ri_branch" "cpu_iss,ipu_bru")
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(define_reservation "rf_insn" "cp1_iss,fpu_fpu")
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(define_reservation "rf_ldmem" "cp1_iss,fpu_load")
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; simultaneous reservation of pseudo-unit keeps cp1 fpu tied
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; up until long cycle insn is finished...
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(define_reservation "rf_multi1" "rf_insn+fpu_iter")
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;;
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;; The ordering of the instruction-execution-path/resource-usage
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;; descriptions (also known as reservation RTL) is roughly ordered
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;; based on the define attribute RTL for the "type" classification.
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;; When modifying, remember that the first test that matches is the
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;; reservation used!
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;;
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(define_insn_reservation "ir_sr70_unknown" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "unknown"))
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"serial_dispatch")
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;; Assume prediction fails.
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(define_insn_reservation "ir_sr70_branch" 6
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "branch,jump,call"))
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"ri_branch")
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(define_insn_reservation "ir_sr70_load" 2
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "load"))
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"ri_mem")
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(define_insn_reservation "ir_sr70_store" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "store"))
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"ri_mem")
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;;
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;; float loads/stores flow through both cpu and cp1...
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;;
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(define_insn_reservation "ir_sr70_fload" 9
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fpload,fpidxload"))
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"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
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(define_insn_reservation "ir_sr70_fstore" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fpstore,fpidxstore"))
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"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
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;; This reservation is for conditional move based on integer
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;; or floating point CC.
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(define_insn_reservation "ir_sr70_condmove" 4
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "condmove"))
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"ri_insns")
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;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
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;; are different. Like float load/store, these insns use multiple
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;; resources simultaneously
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(define_insn_reservation "ir_sr70_xfer_from" 6
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "mfc"))
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"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
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(define_insn_reservation "ir_sr70_xfer_to" 9
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "mtc"))
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"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
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(define_insn_reservation "ir_sr70_hilo" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "mthilo,mfhilo"))
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"ri_insns")
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(define_insn_reservation "ir_sr70_arith" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,trap"))
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"ri_insns")
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;; emulate repeat (dispatch stall) by spending extra cycle(s) in
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;; in iter unit
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(define_insn_reservation "ir_sr70_imul_si" 4
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "imul,imul3,imadd")
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(eq_attr "mode" "SI")))
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"ri_alux,ipu_alux,ipu_macc_iter")
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(define_insn_reservation "ir_sr70_imul_di" 6
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "imul,imul3,imadd")
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(eq_attr "mode" "DI")))
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"ri_alux,ipu_alux,(ipu_macc_iter*3)")
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;; Divide algorithm is early out with best latency of 7 pcycles.
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;; Use worst case for scheduling purposes.
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(define_insn_reservation "ir_sr70_idiv_si" 41
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "SI")))
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"ri_alux,ipu_alux,(ipu_macc_iter*38)")
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(define_insn_reservation "ir_sr70_idiv_di" 73
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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"ri_alux,ipu_alux,(ipu_macc_iter*70)")
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;; extra reservations of fpu_fpu are for repeat latency
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(define_insn_reservation "ir_sr70_fadd_sf" 8
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "fadd")
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(eq_attr "mode" "SF")))
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"rf_insn,fpu_fpu")
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(define_insn_reservation "ir_sr70_fadd_df" 10
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "fadd")
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(eq_attr "mode" "DF")))
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"rf_insn,fpu_fpu")
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;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
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;; with the sub or add.
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(define_insn_reservation "ir_sr70_fmul_sf" 8
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"rf_insn,fpu_fpu")
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;; tie up the fpu unit to emulate the balance for the "repeat
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;; rate" of 8 (2 are spent in the iss unit)
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(define_insn_reservation "ir_sr70_fmul_df" 16
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"rf_insn,fpu_fpu*6")
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;; RECIP insn uses same type attr as div, and for SR3, has same
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;; timings for double. However, single RECIP has a latency of
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;; 28 -- only way to fix this is to introduce new insn attrs.
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;; cycles spent in iter unit are designed to satisfy balance
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;; of "repeat" latency after insn uses up rf_multi1 reservation
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(define_insn_reservation "ir_sr70_fdiv_sf" 60
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "fdiv,frdiv")
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(eq_attr "mode" "SF")))
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"rf_multi1+(fpu_iter*51)")
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(define_insn_reservation "ir_sr70_fdiv_df" 120
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "fdiv,frdiv")
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(eq_attr "mode" "DF")))
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"rf_multi1+(fpu_iter*109)")
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(define_insn_reservation "ir_sr70_fabs" 4
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fabs,fneg,fmove"))
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"rf_insn,fpu_fpu")
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(define_insn_reservation "ir_sr70_fcmp" 10
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fcmp"))
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"rf_insn,fpu_fpu")
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;; "fcvt" type attribute covers a number of diff insns, most have the same
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;; latency descriptions, a few vary. We use the
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;; most common timing (which is also worst case).
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(define_insn_reservation "ir_sr70_fcvt" 12
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fcvt"))
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"rf_insn,fpu_fpu*4")
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(define_insn_reservation "ir_sr70_fsqrt_sf" 62
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "fsqrt")
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(eq_attr "mode" "SF")))
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"rf_multi1+(fpu_iter*53)")
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(define_insn_reservation "ir_sr70_fsqrt_df" 122
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "fsqrt")
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(eq_attr "mode" "DF")))
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"rf_multi1+(fpu_iter*111)")
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(define_insn_reservation "ir_sr70_frsqrt_sf" 48
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "SF")))
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"rf_multi1+(fpu_iter*39)")
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(define_insn_reservation "ir_sr70_frsqrt_df" 240
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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"rf_multi1+(fpu_iter*229)")
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(define_insn_reservation "ir_sr70_multi" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "multi"))
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"serial_dispatch")
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(define_insn_reservation "ir_sr70_nop" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "nop"))
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"ri_insns")
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