292 lines
9.7 KiB
Markdown
292 lines
9.7 KiB
Markdown
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;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005, 2007, 2008
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Predicates
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; TRUE for any valid operand. We do this because general_operand
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; refuses to match volatile memory refs.
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(define_predicate "m32c_any_operand"
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(ior (match_operand 0 "general_operand")
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(match_operand 1 "memory_operand"))
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{
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return ! m32c_illegal_subreg_p (op);
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}
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)
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; Likewise for nonimmediate_operand.
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(define_predicate "m32c_nonimmediate_operand"
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(ior (match_operand 0 "nonimmediate_operand")
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(match_operand 1 "memory_operand")))
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; TRUE if the operand is a pseudo-register.
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(define_predicate "m32c_pseudo"
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(ior (and (match_code "reg")
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(match_test "REGNO(op) >= FIRST_PSEUDO_REGISTER"))
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(and (match_code "subreg")
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(and (match_test "GET_CODE (XEXP (op, 0)) == REG")
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(match_test "REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER")))))
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; Returning true causes many predicates to NOT match. We allow
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; subregs for type changing, but not for size changing.
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(define_predicate "m32c_wide_subreg"
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(and (match_code "subreg")
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(not (match_operand 0 "m32c_pseudo")))
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{
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unsigned int sizeo = GET_MODE_SIZE (GET_MODE (op));
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unsigned int sizei = GET_MODE_SIZE (GET_MODE (XEXP (op, 0)));
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sizeo = (sizeo + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
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sizei = (sizei + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
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return sizeo != sizei;
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})
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; TRUE for r0 through r3, or a pseudo that reload could put in r0
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; through r3 (likewise for the next couple too)
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(define_predicate "r0123_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO(op) <= R3_REGNO"))))
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; TRUE for r0
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(define_predicate "m32c_r0_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO(op) == R0_REGNO"))))
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; TRUE for r1
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(define_predicate "m32c_r1_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO(op) == R1_REGNO"))))
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; TRUE for HL_CLASS (r0 or r1)
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(define_predicate "m32c_hl_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO(op) == R0_REGNO || REGNO(op) == R1_REGNO"))))
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; TRUE for r2
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(define_predicate "m32c_r2_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO(op) == R2_REGNO"))))
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; TRUE for r3
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(define_predicate "m32c_r3_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO(op) == R3_REGNO"))))
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; TRUE for any general operand except r2.
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(define_predicate "m32c_notr2_operand"
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(and (match_operand 0 "general_operand")
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(ior (not (match_code "reg"))
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(match_test "REGNO(op) != R2_REGNO"))))
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; TRUE for the stack pointer.
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(define_predicate "m32c_sp_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO(op) == SP_REGNO"))))
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; TRUE for control registers.
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(define_predicate "cr_operand"
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(match_code "reg")
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"return (REGNO (op) >= SB_REGNO
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&& REGNO (op) <= FLG_REGNO);")
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; TRUE for $a0 or $a1.
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(define_predicate "a_operand"
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(and (match_code "reg")
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(match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO")))
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; TRUE for $a0 or $a1 or a pseudo
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(define_predicate "ap_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO"))))
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; TRUE for r0 through r3, or a0 or a1.
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(define_predicate "ra_operand"
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(and (and (match_operand 0 "register_operand" "")
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(not (match_operand 1 "cr_operand" "")))
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(not (match_operand 2 "m32c_wide_subreg" ""))))
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; Likewise, plus TRUE for memory references.
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(define_predicate "mra_operand"
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(and (and (match_operand 0 "nonimmediate_operand" "")
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(not (match_operand 1 "cr_operand" "")))
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(not (match_operand 2 "m32c_wide_subreg" ""))))
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; Likewise, plus TRUE for subregs.
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(define_predicate "mras_operand"
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(and (match_operand 0 "nonimmediate_operand" "")
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(not (match_operand 1 "cr_operand" ""))))
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; As above, but no push/pop operations
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(define_predicate "mra_nopp_operand"
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(match_operand 0 "mra_operand" "")
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{
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if (GET_CODE (op) == MEM
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&& (GET_CODE (XEXP (op, 0)) == PRE_DEC
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|| (GET_CODE (XEXP (op, 0)) == POST_INC)))
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return 0;
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return 1;
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})
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; TRUE for memory, r0..r3, a0..a1, or immediates.
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(define_predicate "mrai_operand"
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(and (and (match_operand 0 "m32c_any_operand" "")
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(not (match_operand 1 "cr_operand" "")))
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(not (match_operand 2 "m32c_wide_subreg" ""))))
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; Likewise, plus true for subregs.
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(define_predicate "mrasi_operand"
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(and (match_operand 0 "general_operand" "")
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(not (match_operand 1 "cr_operand" ""))))
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; TRUE for r0..r3 or memory.
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(define_predicate "mr_operand"
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(and (match_operand 0 "mra_operand" "")
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(not (match_operand 1 "a_operand" ""))))
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; TRUE for a0..a1 or memory.
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(define_predicate "ma_operand"
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(ior (match_operand 0 "a_operand" "")
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(match_operand 1 "memory_operand" "")))
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; TRUE for memory operands that are not indexed
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(define_predicate "memsym_operand"
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(and (match_operand 0 "memory_operand" "")
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(match_test "m32c_extra_constraint_p (op, 'S', \"Si\")")))
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; TRUE for memory operands with small integer addresses
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(define_predicate "memimmed_operand"
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(and (match_operand 0 "memory_operand" "")
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(match_test "m32c_extra_constraint_p (op, 'S', \"Sp\")")))
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; TRUE for r1h. This is complicated since r1h isn't a register GCC
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; normally knows about.
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(define_predicate "r1h_operand"
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(match_code "zero_extract")
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{
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rtx reg = XEXP (op, 0);
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rtx size = XEXP (op, 1);
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rtx pos = XEXP (op, 2);
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return (GET_CODE (reg) == REG
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&& REGNO (reg) == R1_REGNO
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&& GET_CODE (size) == CONST_INT
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&& INTVAL (size) == 8
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&& GET_CODE (pos) == CONST_INT
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&& INTVAL (pos) == 8);
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})
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; TRUE if we can shift by this amount. Constant shift counts have a
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; limited range.
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(define_predicate "shiftcount_operand"
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(ior (match_operand 0 "mra_operand" "")
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(and (match_operand 2 "const_int_operand" "")
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(match_test "-8 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 8"))))
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(define_predicate "longshiftcount_operand"
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(ior (match_operand 0 "mra_operand" "")
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(and (match_operand 2 "const_int_operand" "")
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(match_test "-32 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 32"))))
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; TRUE for r0..r3, a0..a1, or sp.
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(define_predicate "mra_or_sp_operand"
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(and (ior (match_operand 0 "mra_operand")
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(match_operand 1 "m32c_sp_operand"))
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(not (match_operand 2 "m32c_wide_subreg" ""))))
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; TRUE for r2 or r3.
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(define_predicate "m32c_r2r3_operand"
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(ior (and (match_code "reg")
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(ior (match_test "REGNO(op) == R2_REGNO")
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(match_test "REGNO(op) == R3_REGNO")))
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(and (match_code "subreg")
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(match_test "GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)"))))
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; Likewise, plus TRUE for a0..a1.
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(define_predicate "m32c_r2r3a_operand"
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(ior (match_operand 0 "m32c_r2r3_operand" "")
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(match_operand 0 "a_operand" "")))
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; These two are only for movqi - no subreg limit
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(define_predicate "mra_qi_operand"
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(and (and (match_operand 0 "m32c_nonimmediate_operand" "")
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(not (match_operand 1 "cr_operand" "")))
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(not (match_operand 1 "m32c_r2r3a_operand" ""))))
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(define_predicate "mrai_qi_operand"
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(and (and (match_operand 0 "m32c_any_operand" "")
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(not (match_operand 1 "cr_operand" "")))
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(not (match_operand 1 "m32c_r2r3a_operand" ""))))
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(define_predicate "a_qi_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(match_operand 1 "a_operand" "")))
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; TRUE for comparisons we support.
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(define_predicate "m32c_cmp_operator"
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(match_code "eq,ne,gt,gtu,lt,ltu,ge,geu,le,leu"))
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(define_predicate "m32c_eqne_operator"
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(match_code "eq,ne"))
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; TRUE for mem0
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(define_predicate "m32c_mem0_operand"
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(ior (match_operand 0 "m32c_pseudo" "")
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(and (match_code "reg")
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(match_test "REGNO(op) == MEM0_REGNO"))))
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; TRUE for things the call patterns can return.
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(define_predicate "m32c_return_operand"
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(ior (match_operand 0 "m32c_r0_operand")
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(ior (match_operand 0 "m32c_mem0_operand")
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(match_code "parallel"))))
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; TRUE for constants we can multiply pointers by
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(define_predicate "m32c_psi_scale"
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(and (match_operand 0 "const_int_operand")
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(match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")")))
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; TRUE for one bit set (bit) or clear (mask) out of N bits.
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(define_predicate "m32c_1bit8_operand"
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(and (match_operand 0 "const_int_operand")
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(match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")")))
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(define_predicate "m32c_1bit16_operand"
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(and (match_operand 0 "const_int_operand")
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(match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilw\")")))
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(define_predicate "m32c_1mask8_operand"
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(and (match_operand 0 "const_int_operand")
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(match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"ImB\")")))
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(define_predicate "m32c_1mask16_operand"
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(and (match_operand 0 "const_int_operand")
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(match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Imw\")")))
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