796 lines
28 KiB
Markdown
796 lines
28 KiB
Markdown
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;; Atom Scheduling
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;; Copyright (C) 2009 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;
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;; Atom is an in-order core with two integer pipelines.
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(define_attr "atom_unit" "sishuf,simul,jeu,complex,other"
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(const_string "other"))
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(define_attr "atom_sse_attr" "rcp,movdup,lfence,fence,prefetch,sqrt,mxcsr,other"
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(const_string "other"))
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(define_automaton "atom")
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;; Atom has two ports: port 0 and port 1 connecting to all execution units
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(define_cpu_unit "atom-port-0,atom-port-1" "atom")
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;; EU: Execution Unit
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;; Atom EUs are connected by port 0 or port 1.
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(define_cpu_unit "atom-eu-0, atom-eu-1,
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atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4"
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"atom")
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;; Some EUs have duplicated copied and can be accessed via either
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;; port 0 or port 1
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;; (define_reservation "atom-port-either" "(atom-port-0 | atom-port-1)")
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;;; Some instructions is dual-pipe execution, need both ports
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;;; Complex multi-op macro-instructoins need both ports and all EUs
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(define_reservation "atom-port-dual" "(atom-port-0 + atom-port-1)")
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(define_reservation "atom-all-eu" "(atom-eu-0 + atom-eu-1 +
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atom-imul-1 + atom-imul-2 + atom-imul-3 +
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atom-imul-4)")
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;;; Most of simple instructions have 1 cycle latency. Some of them
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;;; issue in port 0, some in port 0 and some in either port.
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(define_reservation "atom-simple-0" "(atom-port-0 + atom-eu-0)")
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(define_reservation "atom-simple-1" "(atom-port-1 + atom-eu-1)")
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(define_reservation "atom-simple-either" "(atom-simple-0 | atom-simple-1)")
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;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput
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(define_reservation "atom-eu-0-3-1" "(atom-port-0 + atom-eu-0, nothing*2)")
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;;; fmul insn can have 4 or 5 cycles latency
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(define_reservation "atom-fmul-5c" "(atom-port-0 + atom-eu-0), nothing*4")
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(define_reservation "atom-fmul-4c" "(atom-port-0 + atom-eu-0), nothing*3")
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;;; fadd can has 5 cycles latency depends on instruction forms
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(define_reservation "atom-fadd-5c" "(atom-port-1 + atom-eu-1), nothing*5")
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;;; imul insn has 5 cycles latency
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(define_reservation "atom-imul-32"
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"atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4,
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atom-port-0")
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;;; imul instruction excludes other non-FP instructions.
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(exclusion_set "atom-eu-0, atom-eu-1"
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"atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4")
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;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on
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;;; instruction forms
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(define_reservation "atom-dual-1c" "(atom-port-dual + atom-eu-0 + atom-eu-1)")
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(define_reservation "atom-dual-2c"
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"(atom-port-dual + atom-eu-0 + atom-eu-1, nothing)")
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(define_reservation "atom-dual-5c"
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"(atom-port-dual + atom-eu-0 + atom-eu-1, nothing*4)")
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;;; Complex macro-instruction has variants of latency, and uses both ports.
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(define_reservation "atom-complex" "(atom-port-dual + atom-all-eu)")
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(define_insn_reservation "atom_other" 9
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "other")
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(eq_attr "atom_unit" "!jeu")))
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"atom-complex, atom-all-eu*8")
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;; return has type "other" with atom_unit "jeu"
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(define_insn_reservation "atom_other_2" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "other")
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(eq_attr "atom_unit" "jeu")))
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"atom-dual-1c")
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(define_insn_reservation "atom_multi" 9
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(and (eq_attr "cpu" "atom")
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(eq_attr "type" "multi"))
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"atom-complex, atom-all-eu*8")
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;; Normal alu insns without carry
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(define_insn_reservation "atom_alu" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu")
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(and (eq_attr "memory" "none")
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(eq_attr "use_carry" "0"))))
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"atom-simple-either")
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;; Normal alu insns without carry
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(define_insn_reservation "atom_alu_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu")
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(and (eq_attr "memory" "!none")
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(eq_attr "use_carry" "0"))))
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"atom-simple-either")
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;; Alu insn consuming CF, such as add/sbb
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(define_insn_reservation "atom_alu_carry" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu")
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(and (eq_attr "memory" "none")
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(eq_attr "use_carry" "1"))))
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"atom-simple-either")
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;; Alu insn consuming CF, such as add/sbb
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(define_insn_reservation "atom_alu_carry_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu")
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(and (eq_attr "memory" "!none")
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(eq_attr "use_carry" "1"))))
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"atom-simple-either")
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(define_insn_reservation "atom_alu1" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu1")
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(eq_attr "memory" "none")))
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"atom-simple-either")
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(define_insn_reservation "atom_alu1_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu1")
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(eq_attr "memory" "!none")))
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"atom-simple-either")
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(define_insn_reservation "atom_negnot" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "negnot")
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(eq_attr "memory" "none")))
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"atom-simple-either")
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(define_insn_reservation "atom_negnot_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "negnot")
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(eq_attr "memory" "!none")))
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"atom-simple-either")
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(define_insn_reservation "atom_imov" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "none")))
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"atom-simple-either")
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(define_insn_reservation "atom_imov_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "!none")))
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"atom-simple-either")
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;; 16<-16, 32<-32
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(define_insn_reservation "atom_imovx" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (eq_attr "memory" "none")
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(ior (and (match_operand:HI 0 "register_operand")
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(match_operand:HI 1 "general_operand"))
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(and (match_operand:SI 0 "register_operand")
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(match_operand:SI 1 "general_operand"))))))
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"atom-simple-either")
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;; 16<-16, 32<-32, mem
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(define_insn_reservation "atom_imovx_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (eq_attr "memory" "!none")
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(ior (and (match_operand:HI 0 "register_operand")
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(match_operand:HI 1 "general_operand"))
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(and (match_operand:SI 0 "register_operand")
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(match_operand:SI 1 "general_operand"))))))
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"atom-simple-either")
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;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8
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(define_insn_reservation "atom_imovx_2" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (eq_attr "memory" "none")
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(ior (match_operand:QI 0 "register_operand")
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(ior (and (match_operand:SI 0 "register_operand")
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(not (match_operand:SI 1 "general_operand")))
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(match_operand:DI 0 "register_operand"))))))
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"atom-simple-0")
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;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem
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(define_insn_reservation "atom_imovx_2_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (eq_attr "memory" "!none")
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(ior (match_operand:QI 0 "register_operand")
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(ior (and (match_operand:SI 0 "register_operand")
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(not (match_operand:SI 1 "general_operand")))
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(match_operand:DI 0 "register_operand"))))))
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"atom-simple-0")
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;; 16<-8
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(define_insn_reservation "atom_imovx_3" 3
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (match_operand:HI 0 "register_operand")
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(match_operand:QI 1 "general_operand"))))
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"atom-complex, atom-all-eu*2")
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(define_insn_reservation "atom_lea" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "lea")
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(eq_attr "mode" "!HI")))
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"atom-simple-either")
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;; lea 16bit address is complex insn
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(define_insn_reservation "atom_lea_2" 2
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "lea")
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(eq_attr "mode" "HI")))
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"atom-complex, atom-all-eu")
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(define_insn_reservation "atom_incdec" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "incdec")
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(eq_attr "memory" "none")))
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"atom-simple-either")
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(define_insn_reservation "atom_incdec_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "incdec")
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(eq_attr "memory" "!none")))
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"atom-simple-either")
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;; simple shift instruction use SHIFT eu, none memory
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(define_insn_reservation "atom_ishift" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift")
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(and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))))
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"atom-simple-0")
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;; simple shift instruction use SHIFT eu, memory
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(define_insn_reservation "atom_ishift_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift")
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(and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0"))))
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"atom-simple-0")
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;; DF shift (prefixed with 0f) is complex insn with latency of 7 cycles
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(define_insn_reservation "atom_ishift_3" 7
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift")
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(eq_attr "prefix_0f" "1")))
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"atom-complex, atom-all-eu*6")
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(define_insn_reservation "atom_ishift1" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift1")
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(eq_attr "memory" "none")))
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"atom-simple-0")
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(define_insn_reservation "atom_ishift1_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift1")
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(eq_attr "memory" "!none")))
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"atom-simple-0")
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(define_insn_reservation "atom_rotate" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "rotate")
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(eq_attr "memory" "none")))
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"atom-simple-0")
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(define_insn_reservation "atom_rotate_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "rotate")
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(eq_attr "memory" "!none")))
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"atom-simple-0")
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(define_insn_reservation "atom_rotate1" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "rotate1")
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(eq_attr "memory" "none")))
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"atom-simple-0")
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(define_insn_reservation "atom_rotate1_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "rotate1")
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(eq_attr "memory" "!none")))
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"atom-simple-0")
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(define_insn_reservation "atom_imul" 5
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imul")
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(and (eq_attr "memory" "none") (eq_attr "mode" "SI"))))
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"atom-imul-32")
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(define_insn_reservation "atom_imul_mem" 5
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imul")
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(and (eq_attr "memory" "!none") (eq_attr "mode" "SI"))))
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"atom-imul-32")
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;; latency set to 10 as common 64x64 imul
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(define_insn_reservation "atom_imul_3" 10
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imul")
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(eq_attr "mode" "!SI")))
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|
|
"atom-complex, atom-all-eu*9")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_idiv" 65
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "idiv"))
|
||
|
|
"atom-complex, atom-all-eu*32, nothing*32")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_icmp" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "icmp")
|
||
|
|
(eq_attr "memory" "none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_icmp_mem" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "icmp")
|
||
|
|
(eq_attr "memory" "!none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_test" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "test")
|
||
|
|
(eq_attr "memory" "none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_test_mem" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "test")
|
||
|
|
(eq_attr "memory" "!none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_ibr" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ibr")
|
||
|
|
(eq_attr "memory" "!load")))
|
||
|
|
"atom-simple-1")
|
||
|
|
|
||
|
|
;; complex if jump target is from address
|
||
|
|
(define_insn_reservation "atom_ibr_2" 2
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ibr")
|
||
|
|
(eq_attr "memory" "load")))
|
||
|
|
"atom-complex, atom-all-eu")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_setcc" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "setcc")
|
||
|
|
(eq_attr "memory" "!store")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
;; 2 cycles complex if target is in memory
|
||
|
|
(define_insn_reservation "atom_setcc_2" 2
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "setcc")
|
||
|
|
(eq_attr "memory" "store")))
|
||
|
|
"atom-complex, atom-all-eu")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_icmov" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "icmov")
|
||
|
|
(eq_attr "memory" "none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_icmov_mem" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "icmov")
|
||
|
|
(eq_attr "memory" "!none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
;; UCODE if segreg, ignored
|
||
|
|
(define_insn_reservation "atom_push" 2
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "push"))
|
||
|
|
"atom-dual-2c")
|
||
|
|
|
||
|
|
;; pop r64 is 1 cycle. UCODE if segreg, ignored
|
||
|
|
(define_insn_reservation "atom_pop" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "pop")
|
||
|
|
(eq_attr "mode" "DI")))
|
||
|
|
"atom-dual-1c")
|
||
|
|
|
||
|
|
;; pop non-r64 is 2 cycles. UCODE if segreg, ignored
|
||
|
|
(define_insn_reservation "atom_pop_2" 2
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "pop")
|
||
|
|
(eq_attr "mode" "!DI")))
|
||
|
|
"atom-dual-2c")
|
||
|
|
|
||
|
|
;; UCODE if segreg, ignored
|
||
|
|
(define_insn_reservation "atom_call" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "call"))
|
||
|
|
"atom-dual-1c")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_callv" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "callv"))
|
||
|
|
"atom-dual-1c")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_leave" 3
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "leave"))
|
||
|
|
"atom-complex, atom-all-eu*2")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_str" 3
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "str"))
|
||
|
|
"atom-complex, atom-all-eu*2")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_sselog" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sselog")
|
||
|
|
(eq_attr "memory" "none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_sselog_mem" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sselog")
|
||
|
|
(eq_attr "memory" "!none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_sselog1" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sselog1")
|
||
|
|
(eq_attr "memory" "none")))
|
||
|
|
"atom-simple-0")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_sselog1_mem" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sselog1")
|
||
|
|
(eq_attr "memory" "!none")))
|
||
|
|
"atom-simple-0")
|
||
|
|
|
||
|
|
;; not pmad, not psad
|
||
|
|
(define_insn_reservation "atom_sseiadd" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseiadd")
|
||
|
|
(and (not (match_operand:V2DI 0 "register_operand"))
|
||
|
|
(and (eq_attr "atom_unit" "!simul")
|
||
|
|
(eq_attr "atom_unit" "!complex")))))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
;; pmad, psad and 64
|
||
|
|
(define_insn_reservation "atom_sseiadd_2" 4
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseiadd")
|
||
|
|
(and (not (match_operand:V2DI 0 "register_operand"))
|
||
|
|
(and (eq_attr "atom_unit" "simul" )
|
||
|
|
(eq_attr "mode" "DI")))))
|
||
|
|
"atom-fmul-4c")
|
||
|
|
|
||
|
|
;; pmad, psad and 128
|
||
|
|
(define_insn_reservation "atom_sseiadd_3" 5
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseiadd")
|
||
|
|
(and (not (match_operand:V2DI 0 "register_operand"))
|
||
|
|
(and (eq_attr "atom_unit" "simul" )
|
||
|
|
(eq_attr "mode" "TI")))))
|
||
|
|
"atom-fmul-5c")
|
||
|
|
|
||
|
|
;; if paddq(64 bit op), phadd/phsub
|
||
|
|
(define_insn_reservation "atom_sseiadd_4" 6
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseiadd")
|
||
|
|
(ior (match_operand:V2DI 0 "register_operand")
|
||
|
|
(eq_attr "atom_unit" "complex"))))
|
||
|
|
"atom-complex, atom-all-eu*5")
|
||
|
|
|
||
|
|
;; if immediate op.
|
||
|
|
(define_insn_reservation "atom_sseishft" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseishft")
|
||
|
|
(and (eq_attr "atom_unit" "!sishuf")
|
||
|
|
(match_operand 2 "immediate_operand"))))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
;; if palignr or psrldq
|
||
|
|
(define_insn_reservation "atom_sseishft_2" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseishft")
|
||
|
|
(and (eq_attr "atom_unit" "sishuf")
|
||
|
|
(match_operand 2 "immediate_operand"))))
|
||
|
|
"atom-simple-0")
|
||
|
|
|
||
|
|
;; if reg/mem op
|
||
|
|
(define_insn_reservation "atom_sseishft_3" 2
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseishft")
|
||
|
|
(not (match_operand 2 "immediate_operand"))))
|
||
|
|
"atom-complex, atom-all-eu")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_sseimul" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "sseimul"))
|
||
|
|
"atom-simple-0")
|
||
|
|
|
||
|
|
;; rcpss or rsqrtss
|
||
|
|
(define_insn_reservation "atom_sse" 4
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sse")
|
||
|
|
(and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF"))))
|
||
|
|
"atom-fmul-4c")
|
||
|
|
|
||
|
|
;; movshdup, movsldup. Suggest to type sseishft
|
||
|
|
(define_insn_reservation "atom_sse_2" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sse")
|
||
|
|
(eq_attr "atom_sse_attr" "movdup")))
|
||
|
|
"atom-simple-0")
|
||
|
|
|
||
|
|
;; lfence
|
||
|
|
(define_insn_reservation "atom_sse_3" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sse")
|
||
|
|
(eq_attr "atom_sse_attr" "lfence")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
;; sfence,clflush,mfence, prefetch
|
||
|
|
(define_insn_reservation "atom_sse_4" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sse")
|
||
|
|
(ior (eq_attr "atom_sse_attr" "fence")
|
||
|
|
(eq_attr "atom_sse_attr" "prefetch"))))
|
||
|
|
"atom-simple-0")
|
||
|
|
|
||
|
|
;; rcpps, rsqrtss, sqrt, ldmxcsr
|
||
|
|
(define_insn_reservation "atom_sse_5" 7
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sse")
|
||
|
|
(ior (ior (eq_attr "atom_sse_attr" "sqrt")
|
||
|
|
(eq_attr "atom_sse_attr" "mxcsr"))
|
||
|
|
(and (eq_attr "atom_sse_attr" "rcp")
|
||
|
|
(eq_attr "mode" "V4SF")))))
|
||
|
|
"atom-complex, atom-all-eu*6")
|
||
|
|
|
||
|
|
;; xmm->xmm
|
||
|
|
(define_insn_reservation "atom_ssemov" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssemov")
|
||
|
|
(and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "xy"))))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
;; reg->xmm
|
||
|
|
(define_insn_reservation "atom_ssemov_2" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssemov")
|
||
|
|
(and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "r"))))
|
||
|
|
"atom-simple-0")
|
||
|
|
|
||
|
|
;; xmm->reg
|
||
|
|
(define_insn_reservation "atom_ssemov_3" 3
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssemov")
|
||
|
|
(and (match_operand 0 "register_operand" "r") (match_operand 1 "register_operand" "xy"))))
|
||
|
|
"atom-eu-0-3-1")
|
||
|
|
|
||
|
|
;; mov mem
|
||
|
|
(define_insn_reservation "atom_ssemov_4" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssemov")
|
||
|
|
(and (eq_attr "movu" "0") (eq_attr "memory" "!none"))))
|
||
|
|
"atom-simple-0")
|
||
|
|
|
||
|
|
;; movu mem
|
||
|
|
(define_insn_reservation "atom_ssemov_5" 2
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssemov")
|
||
|
|
(ior (eq_attr "movu" "1") (eq_attr "memory" "!none"))))
|
||
|
|
"atom-complex, atom-all-eu")
|
||
|
|
|
||
|
|
;; no memory simple
|
||
|
|
(define_insn_reservation "atom_sseadd" 5
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseadd")
|
||
|
|
(and (eq_attr "memory" "none")
|
||
|
|
(and (eq_attr "mode" "!V2DF")
|
||
|
|
(eq_attr "atom_unit" "!complex")))))
|
||
|
|
"atom-fadd-5c")
|
||
|
|
|
||
|
|
;; memory simple
|
||
|
|
(define_insn_reservation "atom_sseadd_mem" 5
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseadd")
|
||
|
|
(and (eq_attr "memory" "!none")
|
||
|
|
(and (eq_attr "mode" "!V2DF")
|
||
|
|
(eq_attr "atom_unit" "!complex")))))
|
||
|
|
"atom-dual-5c")
|
||
|
|
|
||
|
|
;; maxps, minps, *pd, hadd, hsub
|
||
|
|
(define_insn_reservation "atom_sseadd_3" 8
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseadd")
|
||
|
|
(ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex"))))
|
||
|
|
"atom-complex, atom-all-eu*7")
|
||
|
|
|
||
|
|
;; Except dppd/dpps
|
||
|
|
(define_insn_reservation "atom_ssemul" 5
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssemul")
|
||
|
|
(eq_attr "mode" "!SF")))
|
||
|
|
"atom-fmul-5c")
|
||
|
|
|
||
|
|
;; Except dppd/dpps, 4 cycle if mulss
|
||
|
|
(define_insn_reservation "atom_ssemul_2" 4
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssemul")
|
||
|
|
(eq_attr "mode" "SF")))
|
||
|
|
"atom-fmul-4c")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_ssecmp" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "ssecmp"))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_ssecomi" 10
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "ssecomi"))
|
||
|
|
"atom-complex, atom-all-eu*9")
|
||
|
|
|
||
|
|
;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi
|
||
|
|
(define_insn_reservation "atom_ssecvt" 5
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssecvt")
|
||
|
|
(ior (and (match_operand:V2SI 0 "register_operand")
|
||
|
|
(match_operand:V4SF 1 "register_operand"))
|
||
|
|
(and (match_operand:V4SF 0 "register_operand")
|
||
|
|
(match_operand:V2SI 1 "register_operand")))))
|
||
|
|
"atom-fadd-5c")
|
||
|
|
|
||
|
|
;; memory and cvtpi2ps, cvtps2pi, cvttps2pi
|
||
|
|
(define_insn_reservation "atom_ssecvt_2" 5
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssecvt")
|
||
|
|
(ior (and (match_operand:V2SI 0 "register_operand")
|
||
|
|
(match_operand:V4SF 1 "memory_operand"))
|
||
|
|
(and (match_operand:V4SF 0 "register_operand")
|
||
|
|
(match_operand:V2SI 1 "memory_operand")))))
|
||
|
|
"atom-dual-5c")
|
||
|
|
|
||
|
|
;; otherwise. 7 cycles average for cvtss2sd
|
||
|
|
(define_insn_reservation "atom_ssecvt_3" 7
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "ssecvt")
|
||
|
|
(not (ior (and (match_operand:V2SI 0 "register_operand")
|
||
|
|
(match_operand:V4SF 1 "nonimmediate_operand"))
|
||
|
|
(and (match_operand:V4SF 0 "register_operand")
|
||
|
|
(match_operand:V2SI 1 "nonimmediate_operand"))))))
|
||
|
|
"atom-complex, atom-all-eu*6")
|
||
|
|
|
||
|
|
;; memory and cvtsi2sd
|
||
|
|
(define_insn_reservation "atom_sseicvt" 5
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseicvt")
|
||
|
|
(and (match_operand:V2DF 0 "register_operand")
|
||
|
|
(match_operand:SI 1 "memory_operand"))))
|
||
|
|
"atom-dual-5c")
|
||
|
|
|
||
|
|
;; otherwise. 8 cycles average for cvtsd2si
|
||
|
|
(define_insn_reservation "atom_sseicvt_2" 8
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "sseicvt")
|
||
|
|
(not (and (match_operand:V2DF 0 "register_operand")
|
||
|
|
(match_operand:SI 1 "memory_operand")))))
|
||
|
|
"atom-complex, atom-all-eu*7")
|
||
|
|
|
||
|
|
(define_insn_reservation "atom_ssediv" 62
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(eq_attr "type" "ssediv"))
|
||
|
|
"atom-complex, atom-all-eu*12, nothing*49")
|
||
|
|
|
||
|
|
;; simple for fmov
|
||
|
|
(define_insn_reservation "atom_fmov" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "fmov")
|
||
|
|
(eq_attr "memory" "none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
;; simple for fmov
|
||
|
|
(define_insn_reservation "atom_fmov_mem" 1
|
||
|
|
(and (eq_attr "cpu" "atom")
|
||
|
|
(and (eq_attr "type" "fmov")
|
||
|
|
(eq_attr "memory" "!none")))
|
||
|
|
"atom-simple-either")
|
||
|
|
|
||
|
|
;; Define bypass here
|
||
|
|
|
||
|
|
;; There will be no stall from lea to non-mem EX insns
|
||
|
|
(define_bypass 0 "atom_lea"
|
||
|
|
"atom_alu_carry,
|
||
|
|
atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
|
||
|
|
atom_incdec, atom_setcc, atom_icmov, atom_pop")
|
||
|
|
|
||
|
|
(define_bypass 0 "atom_lea"
|
||
|
|
"atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
||
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
||
|
|
atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
|
||
|
|
"!ix86_agi_dependent")
|
||
|
|
|
||
|
|
;; There will be 3 cycles stall from EX insns to AGAN insns LEA
|
||
|
|
(define_bypass 4 "atom_alu_carry,
|
||
|
|
atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
|
||
|
|
atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
|
||
|
|
atom_rotate1, atom_setcc, atom_icmov, atom_pop,
|
||
|
|
atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
||
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
||
|
|
atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
|
||
|
|
"atom_lea")
|
||
|
|
|
||
|
|
;; There will be 3 cycles stall from EX insns to insns need addr calculation
|
||
|
|
(define_bypass 4 "atom_alu_carry,
|
||
|
|
atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
|
||
|
|
atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
|
||
|
|
atom_rotate1, atom_setcc, atom_icmov, atom_pop,
|
||
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
||
|
|
atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
||
|
|
atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
|
||
|
|
"atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
||
|
|
atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
|
||
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
||
|
|
atom_imul_mem, atom_icmp_mem,
|
||
|
|
atom_test_mem, atom_icmov_mem, atom_sselog_mem,
|
||
|
|
atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem,
|
||
|
|
atom_ishift_mem, atom_ishift1_mem,
|
||
|
|
atom_rotate_mem, atom_rotate1_mem"
|
||
|
|
"ix86_agi_dependent")
|
||
|
|
|
||
|
|
;; Stall from imul to lea is 8 cycles.
|
||
|
|
(define_bypass 9 "atom_imul, atom_imul_mem" "atom_lea")
|
||
|
|
|
||
|
|
;; Stall from imul to memory address is 8 cycles.
|
||
|
|
(define_bypass 9 "atom_imul, atom_imul_mem"
|
||
|
|
"atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
||
|
|
atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
|
||
|
|
atom_ishift_mem, atom_ishift1_mem, atom_rotate_mem,
|
||
|
|
atom_rotate1_mem, atom_imul_mem, atom_icmp_mem,
|
||
|
|
atom_test_mem, atom_icmov_mem, atom_sselog_mem,
|
||
|
|
atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem"
|
||
|
|
"ix86_agi_dependent")
|
||
|
|
|
||
|
|
;; There will be 0 cycle stall from cmp/test to jcc
|
||
|
|
|
||
|
|
;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
|
||
|
|
(define_bypass 2 "atom_icmp, atom_test, atom_alu, atom_alu_carry,
|
||
|
|
atom_alu1, atom_negnot, atom_incdec, atom_ishift,
|
||
|
|
atom_ishift1, atom_rotate, atom_rotate1"
|
||
|
|
"atom_icmov, atom_alu_carry")
|
||
|
|
|
||
|
|
;; lea to shift count stall is 2 cycles
|
||
|
|
(define_bypass 3 "atom_lea"
|
||
|
|
"atom_ishift, atom_ishift1, atom_rotate, atom_rotate1,
|
||
|
|
atom_ishift_mem, atom_ishift1_mem,
|
||
|
|
atom_rotate_mem, atom_rotate1_mem"
|
||
|
|
"ix86_dep_by_shift_count")
|
||
|
|
|
||
|
|
;; lea to shift source stall is 1 cycle
|
||
|
|
(define_bypass 2 "atom_lea"
|
||
|
|
"atom_ishift, atom_ishift1, atom_rotate, atom_rotate1"
|
||
|
|
"!ix86_dep_by_shift_count")
|
||
|
|
|
||
|
|
;; non-lea to shift count stall is 1 cycle
|
||
|
|
(define_bypass 2 "atom_alu_carry,
|
||
|
|
atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
|
||
|
|
atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
|
||
|
|
atom_rotate1, atom_setcc, atom_icmov, atom_pop,
|
||
|
|
atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
||
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
||
|
|
atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
|
||
|
|
"atom_ishift, atom_ishift1, atom_rotate, atom_rotate1,
|
||
|
|
atom_ishift_mem, atom_ishift1_mem,
|
||
|
|
atom_rotate_mem, atom_rotate1_mem"
|
||
|
|
"ix86_dep_by_shift_count")
|