377 lines
14 KiB
Markdown
377 lines
14 KiB
Markdown
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;; ARM 1136J[F]-S Pipeline Description
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;; Copyright (C) 2003, 2007 Free Software Foundation, Inc.
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;; Written by CodeSourcery, LLC.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>. */
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;; These descriptions are based on the information contained in the
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;; ARM1136JF-S Technical Reference Manual, Copyright (c) 2003 ARM
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;; Limited.
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;;
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;; This automaton provides a pipeline description for the ARM
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;; 1136J-S and 1136JF-S cores.
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;;
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;; The model given here assumes that the condition for all conditional
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;; instructions is "true", i.e., that all of the instructions are
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;; actually executed.
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(define_automaton "arm1136jfs")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Pipelines
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; There are three distinct pipelines (page 1-26 and following):
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;;
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;; - A 4-stage decode pipeline, shared by all three. It has fetch (1),
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;; fetch (2), decode, and issue stages. Since this is always involved,
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;; we do not model it in the scheduler.
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;;
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;; - A 4-stage ALU pipeline. It has shifter, ALU (main integer operations),
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;; and saturation stages. The fourth stage is writeback; see below.
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;;
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;; - A 4-stage multiply-accumulate pipeline. It has three stages, called
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;; MAC1 through MAC3, and a fourth writeback stage.
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;;
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;; The 4th-stage writeback is shared between the ALU and MAC pipelines,
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;; which operate in lockstep. Results from either pipeline will be
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;; moved into the writeback stage. Because the two pipelines operate
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;; in lockstep, we schedule them as a single "execute" pipeline.
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;;
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;; - A 4-stage LSU pipeline. It has address generation, data cache (1),
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;; data cache (2), and writeback stages. (Note that this pipeline,
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;; including the writeback stage, is independent from the ALU & LSU pipes.)
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(define_cpu_unit "e_1,e_2,e_3,e_wb" "arm1136jfs") ; ALU and MAC
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; e_1 = Sh/Mac1, e_2 = ALU/Mac2, e_3 = SAT/Mac3
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(define_cpu_unit "l_a,l_dc1,l_dc2,l_wb" "arm1136jfs") ; Load/Store
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU instructions require eight cycles to execute, and use the ALU
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;; pipeline in each of the eight stages. The results are available
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;; after the alu stage has finished.
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;;
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;; If the destination register is the PC, the pipelines are stalled
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;; for several cycles. That case is not modelled here.
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;; ALU operations with no shifted operand
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(define_insn_reservation "11_alu_op" 2
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "alu"))
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"e_1,e_2,e_3,e_wb")
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;; ALU operations with a shift-by-constant operand
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(define_insn_reservation "11_alu_shift_op" 2
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "alu_shift"))
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"e_1,e_2,e_3,e_wb")
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;; ALU operations with a shift-by-register operand
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;; These really stall in the decoder, in order to read
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;; the shift value in a second cycle. Pretend we take two cycles in
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;; the shift stage.
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(define_insn_reservation "11_alu_shift_reg_op" 3
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "alu_shift_reg"))
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"e_1*2,e_2,e_3,e_wb")
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;; alu_ops can start sooner, if there is no shifter dependency
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(define_bypass 1 "11_alu_op,11_alu_shift_op"
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"11_alu_op")
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(define_bypass 1 "11_alu_op,11_alu_shift_op"
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"11_alu_shift_op"
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"arm_no_early_alu_shift_value_dep")
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(define_bypass 1 "11_alu_op,11_alu_shift_op"
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"11_alu_shift_reg_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 2 "11_alu_shift_reg_op"
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"11_alu_op")
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(define_bypass 2 "11_alu_shift_reg_op"
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"11_alu_shift_op"
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"arm_no_early_alu_shift_value_dep")
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(define_bypass 2 "11_alu_shift_reg_op"
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"11_alu_shift_reg_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 1 "11_alu_op,11_alu_shift_op"
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"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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"arm_no_early_mul_dep")
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(define_bypass 2 "11_alu_shift_reg_op"
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"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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"arm_no_early_mul_dep")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication instructions loop in the first two execute stages until
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;; the instruction has been passed through the multiplier array enough
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;; times.
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;; Multiply and multiply-accumulate results are available after four stages.
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(define_insn_reservation "11_mult1" 4
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "insn" "mul,mla"))
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"e_1*2,e_2,e_3,e_wb")
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;; The *S variants set the condition flags, which requires three more cycles.
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(define_insn_reservation "11_mult2" 4
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "insn" "muls,mlas"))
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"e_1*2,e_2,e_3,e_wb")
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(define_bypass 3 "11_mult1,11_mult2"
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"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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"arm_no_early_mul_dep")
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(define_bypass 3 "11_mult1,11_mult2"
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"11_alu_op")
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(define_bypass 3 "11_mult1,11_mult2"
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"11_alu_shift_op"
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"arm_no_early_alu_shift_value_dep")
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(define_bypass 3 "11_mult1,11_mult2"
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"11_alu_shift_reg_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 3 "11_mult1,11_mult2"
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"11_store1"
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"arm_no_early_store_addr_dep")
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;; Signed and unsigned multiply long results are available across two cycles;
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;; the less significant word is available one cycle before the more significant
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;; word. Here we conservatively wait until both are available, which is
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;; after three iterations and the memory cycle. The same is also true of
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;; the two multiply-accumulate instructions.
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(define_insn_reservation "11_mult3" 5
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "insn" "smull,umull,smlal,umlal"))
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"e_1*3,e_2,e_3,e_wb*2")
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;; The *S variants set the condition flags, which requires three more cycles.
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(define_insn_reservation "11_mult4" 5
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "insn" "smulls,umulls,smlals,umlals"))
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"e_1*3,e_2,e_3,e_wb*2")
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(define_bypass 4 "11_mult3,11_mult4"
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"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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"arm_no_early_mul_dep")
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(define_bypass 4 "11_mult3,11_mult4"
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"11_alu_op")
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(define_bypass 4 "11_mult3,11_mult4"
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"11_alu_shift_op"
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"arm_no_early_alu_shift_value_dep")
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(define_bypass 4 "11_mult3,11_mult4"
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"11_alu_shift_reg_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 4 "11_mult3,11_mult4"
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"11_store1"
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"arm_no_early_store_addr_dep")
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;; Various 16x16->32 multiplies and multiply-accumulates, using combinations
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;; of high and low halves of the argument registers. They take a single
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;; pass through the pipeline and make the result available after three
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;; cycles.
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(define_insn_reservation "11_mult5" 3
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "insn" "smulxy,smlaxy,smulwy,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx"))
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"e_1,e_2,e_3,e_wb")
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(define_bypass 2 "11_mult5"
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"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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"arm_no_early_mul_dep")
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(define_bypass 2 "11_mult5"
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"11_alu_op")
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(define_bypass 2 "11_mult5"
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"11_alu_shift_op"
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"arm_no_early_alu_shift_value_dep")
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(define_bypass 2 "11_mult5"
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"11_alu_shift_reg_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 2 "11_mult5"
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"11_store1"
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"arm_no_early_store_addr_dep")
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;; The same idea, then the 32-bit result is added to a 64-bit quantity.
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(define_insn_reservation "11_mult6" 4
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "insn" "smlalxy"))
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"e_1*2,e_2,e_3,e_wb*2")
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;; Signed 32x32 multiply, then the most significant 32 bits are extracted
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;; and are available after the memory stage.
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(define_insn_reservation "11_mult7" 4
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "insn" "smmul,smmulr"))
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"e_1*2,e_2,e_3,e_wb")
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(define_bypass 3 "11_mult6,11_mult7"
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"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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"arm_no_early_mul_dep")
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(define_bypass 3 "11_mult6,11_mult7"
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"11_alu_op")
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(define_bypass 3 "11_mult6,11_mult7"
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"11_alu_shift_op"
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"arm_no_early_alu_shift_value_dep")
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(define_bypass 3 "11_mult6,11_mult7"
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"11_alu_shift_reg_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 3 "11_mult6,11_mult7"
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"11_store1"
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"arm_no_early_store_addr_dep")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; These vary greatly depending on their arguments and the results of
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;; stat prediction. Cycle count ranges from zero (unconditional branch,
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;; folded dynamic prediction) to seven (incorrect predictions, etc). We
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;; assume an optimal case for now, because the cost of a cache miss
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;; overwhelms the cost of everything else anyhow.
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(define_insn_reservation "11_branches" 0
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "branch"))
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"nothing")
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;; Call latencies are not predictable. A semi-arbitrary very large
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;; number is used as "positive infinity" so that everything should be
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;; finished by the time of return.
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(define_insn_reservation "11_call" 32
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "call"))
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"nothing")
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;; Branches are predicted. A correctly predicted branch will be no
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;; cost, but we're conservative here, and use the timings a
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;; late-register would give us.
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(define_bypass 1 "11_alu_op,11_alu_shift_op"
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"11_branches")
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(define_bypass 2 "11_alu_shift_reg_op"
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"11_branches")
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(define_bypass 2 "11_load1,11_load2"
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"11_branches")
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(define_bypass 3 "11_load34"
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"11_branches")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Load/Store Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The models for load/store instructions do not accurately describe
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;; the difference between operations with a base register writeback.
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;; These models assume that all memory references hit in dcache. Also,
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;; if the PC is one of the registers involved, there are additional stalls
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;; not modelled here. Addressing modes are also not modelled.
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(define_insn_reservation "11_load1" 3
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "load1"))
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"l_a+e_1,l_dc1,l_dc2,l_wb")
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;; Load byte results are not available until the writeback stage, where
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;; the correct byte is extracted.
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(define_insn_reservation "11_loadb" 4
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "load_byte"))
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"l_a+e_1,l_dc1,l_dc2,l_wb")
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(define_insn_reservation "11_store1" 0
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "store1"))
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"l_a+e_1,l_dc1,l_dc2,l_wb")
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;; Load/store double words into adjacent registers. The timing and
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;; latencies are different depending on whether the address is 64-bit
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;; aligned. This model assumes that it is.
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(define_insn_reservation "11_load2" 3
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(and (eq_attr "tune" "arm1136js,arm1136jfs")
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(eq_attr "type" "load2"))
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"l_a+e_1,l_dc1,l_dc2,l_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "11_store2" 0
|
||
|
|
(and (eq_attr "tune" "arm1136js,arm1136jfs")
|
||
|
|
(eq_attr "type" "store2"))
|
||
|
|
"l_a+e_1,l_dc1,l_dc2,l_wb")
|
||
|
|
|
||
|
|
;; Load/store multiple registers. Two registers are stored per cycle.
|
||
|
|
;; Actual timing depends on how many registers are affected, so we
|
||
|
|
;; optimistically schedule a low latency.
|
||
|
|
(define_insn_reservation "11_load34" 4
|
||
|
|
(and (eq_attr "tune" "arm1136js,arm1136jfs")
|
||
|
|
(eq_attr "type" "load3,load4"))
|
||
|
|
"l_a+e_1,l_dc1*2,l_dc2,l_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "11_store34" 0
|
||
|
|
(and (eq_attr "tune" "arm1136js,arm1136jfs")
|
||
|
|
(eq_attr "type" "store3,store4"))
|
||
|
|
"l_a+e_1,l_dc1*2,l_dc2,l_wb")
|
||
|
|
|
||
|
|
;; A store can start immediately after an alu op, if that alu op does
|
||
|
|
;; not provide part of the address to access.
|
||
|
|
(define_bypass 1 "11_alu_op,11_alu_shift_op"
|
||
|
|
"11_store1"
|
||
|
|
"arm_no_early_store_addr_dep")
|
||
|
|
(define_bypass 2 "11_alu_shift_reg_op"
|
||
|
|
"11_store1"
|
||
|
|
"arm_no_early_store_addr_dep")
|
||
|
|
|
||
|
|
;; An alu op can start sooner after a load, if that alu op does not
|
||
|
|
;; have an early register dependency on the load
|
||
|
|
(define_bypass 2 "11_load1"
|
||
|
|
"11_alu_op")
|
||
|
|
(define_bypass 2 "11_load1"
|
||
|
|
"11_alu_shift_op"
|
||
|
|
"arm_no_early_alu_shift_value_dep")
|
||
|
|
(define_bypass 2 "11_load1"
|
||
|
|
"11_alu_shift_reg_op"
|
||
|
|
"arm_no_early_alu_shift_dep")
|
||
|
|
|
||
|
|
(define_bypass 3 "11_loadb"
|
||
|
|
"11_alu_op")
|
||
|
|
(define_bypass 3 "11_loadb"
|
||
|
|
"11_alu_shift_op"
|
||
|
|
"arm_no_early_alu_shift_value_dep")
|
||
|
|
(define_bypass 3 "11_loadb"
|
||
|
|
"11_alu_shift_reg_op"
|
||
|
|
"arm_no_early_alu_shift_dep")
|
||
|
|
|
||
|
|
;; A mul op can start sooner after a load, if that mul op does not
|
||
|
|
;; have an early multiply dependency
|
||
|
|
(define_bypass 2 "11_load1"
|
||
|
|
"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
|
||
|
|
"arm_no_early_mul_dep")
|
||
|
|
(define_bypass 3 "11_load34"
|
||
|
|
"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
|
||
|
|
"arm_no_early_mul_dep")
|
||
|
|
(define_bypass 3 "11_loadb"
|
||
|
|
"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
|
||
|
|
"arm_no_early_mul_dep")
|
||
|
|
|
||
|
|
;; A store can start sooner after a load, if that load does not
|
||
|
|
;; produce part of the address to access
|
||
|
|
(define_bypass 2 "11_load1"
|
||
|
|
"11_store1"
|
||
|
|
"arm_no_early_store_addr_dep")
|
||
|
|
(define_bypass 3 "11_loadb"
|
||
|
|
"11_store1"
|
||
|
|
"arm_no_early_store_addr_dep")
|