487 lines
15 KiB
Markdown
487 lines
15 KiB
Markdown
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;; DFA scheduling description for SH4.
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;; Copyright (C) 2004, 2006, 2007 Free Software Foundation, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Load and store instructions save a cycle if they are aligned on a
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;; four byte boundary. Using a function unit for stores encourages
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;; gcc to separate load and store instructions by one instruction,
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;; which makes it more likely that the linker will be able to word
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;; align them when relaxing.
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;; The following description models the SH4 pipeline using the DFA based
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;; scheduler. The DFA based description is better way to model a
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;; superscalar pipeline as compared to function unit reservation model.
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;; 1. The function unit based model is oriented to describe at most one
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;; unit reservation by each insn. It is difficult to model unit reservations
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;; in multiple pipeline units by same insn. This can be done using DFA
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;; based description.
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;; 2. The execution performance of DFA based scheduler does not depend on
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;; processor complexity.
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;; 3. Writing all unit reservations for an instruction class is a more natural
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;; description of the pipeline and makes the interface to the hazard
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;; recognizer simpler than the old function unit based model.
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;; 4. The DFA model is richer and is a part of greater overall framework
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;; of RCSP.
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;; Two automata are defined to reduce number of states
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;; which a single large automaton will have. (Factoring)
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(define_automaton "inst_pipeline,fpu_pipe")
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;; This unit is basically the decode unit of the processor.
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;; Since SH4 is a dual issue machine,it is as if there are two
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;; units so that any insn can be processed by either one
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;; of the decoding unit.
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(define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
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;; The fixed point arithmetic calculator(?? EX Unit).
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(define_cpu_unit "int" "inst_pipeline")
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;; f1_1 and f1_2 are floating point units.Actually there is
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;; a f1 unit which can overlap with other f1 unit but
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;; not another F1 unit.It is as though there were two
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;; f1 units.
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(define_cpu_unit "f1_1,f1_2" "fpu_pipe")
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;; The floating point units (except FS - F2 always precedes it.)
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(define_cpu_unit "F0,F1,F2,F3" "fpu_pipe")
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;; This is basically the MA unit of SH4
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;; used in LOAD/STORE pipeline.
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(define_cpu_unit "memory" "inst_pipeline")
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;; However, there are LS group insns that don't use it, even ones that
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;; complete in 0 cycles. So we use an extra unit for the issue of LS insns.
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(define_cpu_unit "load_store" "inst_pipeline")
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;; The address calculator used for branch instructions.
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;; This will be reserved after "issue" of branch instructions
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;; and this is to make sure that no two branch instructions
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;; can be issued in parallel.
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(define_cpu_unit "pcr_addrcalc" "inst_pipeline")
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;; ----------------------------------------------------
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;; This reservation is to simplify the dual issue description.
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(define_reservation "issue" "pipe_01|pipe_02")
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;; This is to express the locking of D stage.
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;; Note that the issue of a CO group insn also effectively locks the D stage.
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(define_reservation "d_lock" "pipe_01+pipe_02")
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;; Every FE instruction but fipr / ftrv starts with issue and this.
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(define_reservation "F01" "F0+F1")
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;; This is to simplify description where F1,F2,FS
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;; are used simultaneously.
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(define_reservation "fpu" "F1+F2")
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;; This is to highlight the fact that f1
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;; cannot overlap with F1.
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(exclusion_set "f1_1,f1_2" "F1")
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(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
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;; Although reg moves have a latency of zero
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;; we need to highlight that they use D stage
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;; for one cycle.
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;; Group: MT
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(define_insn_reservation "reg_mov" 0
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "move"))
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"issue")
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;; Group: LS
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(define_insn_reservation "freg_mov" 0
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "fmove"))
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"issue+load_store")
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;; We don't model all pipeline stages; we model the issue ('D') stage
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;; inasmuch as we allow only two instructions to issue simultaneously,
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;; and CO instructions prevent any simultaneous issue of another instruction.
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;; (This uses pipe_01 and pipe_02).
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;; Double issue of EX insns is prevented by using the int unit in the EX stage.
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;; Double issue of EX / BR insns is prevented by using the int unit /
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;; pcr_addrcalc unit in the EX stage.
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;; Double issue of BR / LS instructions is prevented by using the
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;; pcr_addrcalc / load_store unit in the issue cycle.
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;; Double issue of FE instructions is prevented by using F0 in the first
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;; pipeline stage after the first D stage.
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;; There is no need to describe the [ES]X / [MN]A / S stages after a D stage
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;; (except in the cases outlined above), nor to describe the FS stage after
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;; the F2 stage.
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;; Other MT group instructions(1 step operations)
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;; Group: MT
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;; Latency: 1
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;; Issue Rate: 1
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(define_insn_reservation "mt" 1
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "mt_group"))
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"issue")
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;; Fixed Point Arithmetic Instructions(1 step operations)
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;; Group: EX
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;; Latency: 1
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;; Issue Rate: 1
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(define_insn_reservation "sh4_simple_arith" 1
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "insn_class" "ex_group"))
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"issue,int")
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;; Load and store instructions have no alignment peculiarities for the SH4,
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;; but they use the load-store unit, which they share with the fmove type
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;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
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;; Loads have a latency of two.
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;; However, call insns can only paired with a preceding insn, and have
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;; a delay slot, so that we want two more insns to be scheduled between the
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;; load of the function address and the call. This is equivalent to a
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;; latency of three.
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;; ADJUST_COST can only properly handle reductions of the cost, so we
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;; use a latency of three here, which gets multiplied by 10 to yield 30.
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;; We only do this for SImode loads of general registers, to make the work
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;; for ADJUST_COST easier.
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;; Load Store instructions. (MOV.[BWL]@(d,GBR)
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;; Group: LS
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;; Latency: 2
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;; Issue Rate: 1
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(define_insn_reservation "sh4_load" 2
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "load,pcload"))
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"issue+load_store,nothing,memory")
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;; calls / sfuncs need an extra instruction for their delay slot.
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;; Moreover, estimating the latency for SImode loads as 3 will also allow
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;; adjust_cost to meaningfully bump it back up to 3 if they load the shift
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;; count of a dynamic shift.
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(define_insn_reservation "sh4_load_si" 3
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "load_si,pcload_si"))
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"issue+load_store,nothing,memory")
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;; (define_bypass 2 "sh4_load_si" "!sh4_call")
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;; The load latency is upped to three higher if the dependent insn does
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;; double precision computation. We want the 'default' latency to reflect
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;; that increased latency because otherwise the insn priorities won't
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;; allow proper scheduling.
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(define_insn_reservation "sh4_fload" 3
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "fload,pcfload"))
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"issue+load_store,nothing,memory")
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;; (define_bypass 2 "sh4_fload" "!")
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(define_insn_reservation "sh4_store" 1
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "store,fstore"))
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"issue+load_store,nothing,memory")
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(define_insn_reservation "mac_mem" 1
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "mac_mem"))
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"d_lock,nothing,memory")
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;; Load Store instructions.
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;; Group: LS
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;; Latency: 1
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;; Issue Rate: 1
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(define_insn_reservation "sh4_gp_fpul" 1
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "gp_fpul"))
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"issue+load_store")
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;; Load Store instructions.
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;; Group: LS
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;; Latency: 3
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;; Issue Rate: 1
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(define_insn_reservation "sh4_fpul_gp" 3
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "fpul_gp"))
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"issue+load_store")
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;; Branch (BF,BF/S,BT,BT/S,BRA)
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;; Group: BR
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;; Latency when taken: 2 (or 1)
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;; Issue Rate: 1
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;; The latency is 1 when displacement is 0.
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;; We can't really do much with the latency, even if we could express it,
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;; but the pairing restrictions are useful to take into account.
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;; ??? If the branch is likely, we might want to fill the delay slot;
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;; if the branch is likely, but not very likely, should we pretend to use
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;; a resource that CO instructions use, to get a pairable delay slot insn?
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(define_insn_reservation "sh4_branch" 1
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "cbranch,jump"))
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"issue+pcr_addrcalc")
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;; Branch Far (JMP,RTS,BRAF)
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;; Group: CO
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;; Latency: 3
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;; Issue Rate: 2
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;; ??? Scheduling happens before branch shortening, and hence jmp and braf
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;; can't be distinguished from bra for the "jump" pattern.
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(define_insn_reservation "sh4_return" 3
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "return,jump_ind"))
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"d_lock*2")
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;; RTE
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;; Group: CO
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;; Latency: 5
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;; Issue Rate: 5
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;; this instruction can be executed in any of the pipelines
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;; and blocks the pipeline for next 4 stages.
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(define_insn_reservation "sh4_return_from_exp" 5
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "rte"))
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"d_lock*5")
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;; OCBP, OCBWB
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;; Group: CO
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;; Latency: 1-5
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;; Issue Rate: 1
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;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
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;; ocbwb on its own would be "d_lock,nothing,memory*5"
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(define_insn_reservation "ocbwb" 6
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "cwb"))
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"d_lock*2,(d_lock+memory)*3,issue+load_store+memory,memory*2")
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;; LDS to PR,JSR
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;; Group: CO
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;; Latency: 3
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;; Issue Rate: 2
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;; The SX stage is blocked for last 2 cycles.
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;; OTOH, the only time that has an effect for insns generated by the compiler
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;; is when lds to PR is followed by sts from PR - and that is highly unlikely -
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;; or when we are doing a function call - and we don't do inter-function
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;; scheduling. For the function call case, it's really best that we end with
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;; something that models an rts.
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(define_insn_reservation "sh4_lds_to_pr" 3
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "prset") )
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"d_lock*2")
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;; calls introduce a longisch delay that is likely to flush the pipelines
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;; of the caller's instructions. Ordinary functions tend to end with a
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;; load to restore a register (in the delay slot of rts), while sfuncs
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;; tend to end with an EX or MT insn. But that is not actually relevant,
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;; since there are no instructions that contend for memory access early.
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;; We could, of course, provide exact scheduling information for specific
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;; sfuncs, if that should prove useful.
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(define_insn_reservation "sh4_call" 16
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "call,sfunc"))
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"d_lock*16")
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;; LDS.L to PR
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;; Group: CO
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;; Latency: 3
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;; Issue Rate: 2
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;; The SX unit is blocked for last 2 cycles.
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(define_insn_reservation "ldsmem_to_pr" 3
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "pload"))
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"d_lock*2")
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;; STS from PR
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;; Group: CO
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;; Latency: 2
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;; Issue Rate: 2
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;; The SX unit in second and third cycles.
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(define_insn_reservation "sts_from_pr" 2
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "prget"))
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"d_lock*2")
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;; STS.L from PR
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;; Group: CO
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;; Latency: 2
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;; Issue Rate: 2
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(define_insn_reservation "sh4_prstore_mem" 2
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "pstore"))
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"d_lock*2,nothing,memory")
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;; LDS to FPSCR
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;; Group: CO
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;; Latency: 4
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;; Issue Rate: 1
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;; F1 is blocked for last three cycles.
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(define_insn_reservation "fpscr_load" 4
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "gp_fpscr"))
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"d_lock,nothing,F1*3")
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;; LDS.L to FPSCR
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;; Group: CO
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;; Latency: 1 / 4
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;; Latency to update Rn is 1 and latency to update FPSCR is 4
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;; Issue Rate: 1
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;; F1 is blocked for last three cycles.
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(define_insn_reservation "fpscr_load_mem" 4
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "mem_fpscr"))
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"d_lock,nothing,(F1+memory),F1*2")
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;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
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;; Group: CO
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;; Latency: 4 / 4
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;; Issue Rate: 2
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(define_insn_reservation "multi" 4
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(and (eq_attr "pipe_model" "sh4")
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(eq_attr "type" "smpy,dmpy"))
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"d_lock,(d_lock+f1_1),(f1_1|f1_2)*3,F2")
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;; Fixed STS from, and LDS to MACL / MACH
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|
;; Group: CO
|
|||
|
;; Latency: 3
|
|||
|
;; Issue Rate: 1
|
|||
|
|
|||
|
(define_insn_reservation "sh4_mac_gp" 3
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "mac_gp,gp_mac,mem_mac"))
|
|||
|
"d_lock")
|
|||
|
|
|||
|
|
|||
|
;; Single precision floating point computation FCMP/EQ,
|
|||
|
;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG
|
|||
|
;; Group: FE
|
|||
|
;; Latency: 3/4
|
|||
|
;; Issue Rate: 1
|
|||
|
|
|||
|
(define_insn_reservation "fp_arith" 3
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "fp,fp_cmp"))
|
|||
|
"issue,F01,F2")
|
|||
|
|
|||
|
;; We don't model the resource usage of this exactly because that would
|
|||
|
;; introduce a bogus latency.
|
|||
|
(define_insn_reservation "sh4_fpscr_toggle" 1
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "fpscr_toggle"))
|
|||
|
"issue")
|
|||
|
|
|||
|
(define_insn_reservation "fp_arith_ftrc" 3
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "ftrc_s"))
|
|||
|
"issue,F01,F2")
|
|||
|
|
|||
|
(define_bypass 1 "fp_arith_ftrc" "sh4_fpul_gp")
|
|||
|
|
|||
|
;; Single Precision FDIV/SQRT
|
|||
|
;; Group: FE
|
|||
|
;; Latency: 12/13 (FDIV); 11/12 (FSQRT)
|
|||
|
;; Issue Rate: 1
|
|||
|
;; We describe fdiv here; fsqrt is actually one cycle faster.
|
|||
|
|
|||
|
(define_insn_reservation "fp_div" 12
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "fdiv"))
|
|||
|
"issue,F01+F3,F2+F3,F3*7,F1+F3,F2")
|
|||
|
|
|||
|
;; Double Precision floating point computation
|
|||
|
;; (FCNVDS, FCNVSD, FLOAT, FTRC)
|
|||
|
;; Group: FE
|
|||
|
;; Latency: (3,4)/5
|
|||
|
;; Issue Rate: 1
|
|||
|
|
|||
|
(define_insn_reservation "dp_float" 4
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "dfp_conv"))
|
|||
|
"issue,F01,F1+F2,F2")
|
|||
|
|
|||
|
;; Double-precision floating-point (FADD,FMUL,FSUB)
|
|||
|
;; Group: FE
|
|||
|
;; Latency: (7,8)/9
|
|||
|
;; Issue Rate: 1
|
|||
|
|
|||
|
(define_insn_reservation "fp_double_arith" 8
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "dfp_arith,dfp_mul"))
|
|||
|
"issue,F01,F1+F2,fpu*4,F2")
|
|||
|
|
|||
|
;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
|
|||
|
;; Group: CO
|
|||
|
;; Latency: 3/5
|
|||
|
;; Issue Rate: 2
|
|||
|
|
|||
|
(define_insn_reservation "fp_double_cmp" 3
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "dfp_cmp"))
|
|||
|
"d_lock,(d_lock+F01),F1+F2,F2")
|
|||
|
|
|||
|
;; Double precision FDIV/SQRT
|
|||
|
;; Group: FE
|
|||
|
;; Latency: (24,25)/26
|
|||
|
;; Issue Rate: 1
|
|||
|
|
|||
|
(define_insn_reservation "dp_div" 25
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "dfdiv"))
|
|||
|
"issue,F01+F3,F1+F2+F3,F2+F3,F3*16,F1+F3,(fpu+F3)*2,F2")
|
|||
|
|
|||
|
|
|||
|
;; Use the branch-not-taken case to model arith3 insns. For the branch taken
|
|||
|
;; case, we'd get a d_lock instead of issue at the end.
|
|||
|
(define_insn_reservation "arith3" 3
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "arith3"))
|
|||
|
"issue,d_lock+pcr_addrcalc,issue")
|
|||
|
|
|||
|
;; arith3b insns schedule the same no matter if the branch is taken or not.
|
|||
|
(define_insn_reservation "arith3b" 2
|
|||
|
(and (eq_attr "pipe_model" "sh4")
|
|||
|
(eq_attr "type" "arith3"))
|
|||
|
"issue,d_lock+pcr_addrcalc")
|