246 lines
8.9 KiB
Markdown
246 lines
8.9 KiB
Markdown
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;; Pipeline model for ST Microelectronics Loongson-2E/2F cores.
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;; Copyright (C) 2008 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Automaton for integer instructions.
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(define_automaton "ls2_alu")
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;; ALU1 and ALU2.
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;; We need to query these units to adjust round-robin counter.
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(define_query_cpu_unit "ls2_alu1_core,ls2_alu2_core" "ls2_alu")
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;; Pseudo units to help modeling of ALU1/2 round-robin dispatch strategy.
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(define_cpu_unit "ls2_alu1_turn,ls2_alu2_turn" "ls2_alu")
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;; Pseudo units to enable/disable ls2_alu[12]_turn units.
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;; ls2_alu[12]_turn unit can be subscribed only after ls2_alu[12]_turn_enabled
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;; unit is subscribed.
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(define_cpu_unit "ls2_alu1_turn_enabled,ls2_alu2_turn_enabled" "ls2_alu")
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(presence_set "ls2_alu1_turn" "ls2_alu1_turn_enabled")
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(presence_set "ls2_alu2_turn" "ls2_alu2_turn_enabled")
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;; Reservations for ALU1 (ALU2) instructions.
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;; Instruction goes to ALU1 (ALU2) and makes next ALU1/2 instruction to
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;; be dispatched to ALU2 (ALU1).
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(define_reservation "ls2_alu1"
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"(ls2_alu1_core+ls2_alu2_turn_enabled)|ls2_alu1_core")
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(define_reservation "ls2_alu2"
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"(ls2_alu2_core+ls2_alu1_turn_enabled)|ls2_alu2_core")
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;; Reservation for ALU1/2 instructions.
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;; Instruction will go to ALU1 iff ls2_alu1_turn_enabled is subscribed and
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;; switch the turn to ALU2 by subscribing ls2_alu2_turn_enabled.
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;; Or to ALU2 otherwise.
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(define_reservation "ls2_alu"
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"(ls2_alu1_core+ls2_alu1_turn+ls2_alu2_turn_enabled)
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|(ls2_alu1_core+ls2_alu1_turn)
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|(ls2_alu2_core+ls2_alu2_turn+ls2_alu1_turn_enabled)
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|(ls2_alu2_core+ls2_alu2_turn)")
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;; Automaton for floating-point instructions.
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(define_automaton "ls2_falu")
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;; FALU1 and FALU2.
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;; We need to query these units to adjust round-robin counter.
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(define_query_cpu_unit "ls2_falu1_core,ls2_falu2_core" "ls2_falu")
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;; Pseudo units to help modeling of FALU1/2 round-robin dispatch strategy.
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(define_cpu_unit "ls2_falu1_turn,ls2_falu2_turn" "ls2_falu")
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;; Pseudo units to enable/disable ls2_falu[12]_turn units.
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;; ls2_falu[12]_turn unit can be subscribed only after
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;; ls2_falu[12]_turn_enabled unit is subscribed.
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(define_cpu_unit "ls2_falu1_turn_enabled,ls2_falu2_turn_enabled" "ls2_falu")
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(presence_set "ls2_falu1_turn" "ls2_falu1_turn_enabled")
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(presence_set "ls2_falu2_turn" "ls2_falu2_turn_enabled")
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;; Reservations for FALU1 (FALU2) instructions.
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;; Instruction goes to FALU1 (FALU2) and makes next FALU1/2 instruction to
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;; be dispatched to FALU2 (FALU1).
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(define_reservation "ls2_falu1"
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"(ls2_falu1_core+ls2_falu2_turn_enabled)|ls2_falu1_core")
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(define_reservation "ls2_falu2"
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"(ls2_falu2_core+ls2_falu1_turn_enabled)|ls2_falu2_core")
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;; Reservation for FALU1/2 instructions.
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;; Instruction will go to FALU1 iff ls2_falu1_turn_enabled is subscribed and
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;; switch the turn to FALU2 by subscribing ls2_falu2_turn_enabled.
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;; Or to FALU2 otherwise.
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(define_reservation "ls2_falu"
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"(ls2_falu1+ls2_falu1_turn+ls2_falu2_turn_enabled)
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|(ls2_falu1+ls2_falu1_turn)
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|(ls2_falu2+ls2_falu2_turn+ls2_falu1_turn_enabled)
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|(ls2_falu2+ls2_falu2_turn)")
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;; The following 4 instructions each subscribe one of
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;; ls2_[f]alu{1,2}_turn_enabled units according to this attribute.
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;; These instructions are used in mips.c: sched_ls2_dfa_post_advance_cycle.
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(define_attr "ls2_turn_type" "alu1,alu2,falu1,falu2,unknown"
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(const_string "unknown"))
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;; Subscribe ls2_alu1_turn_enabled.
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(define_insn "ls2_alu1_turn_enabled_insn"
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[(unspec [(const_int 0)] UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN)]
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"TUNE_LOONGSON_2EF"
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{ gcc_unreachable (); }
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[(set_attr "ls2_turn_type" "alu1")])
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(define_insn_reservation "ls2_alu1_turn_enabled" 0
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(eq_attr "ls2_turn_type" "alu1")
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"ls2_alu1_turn_enabled")
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;; Subscribe ls2_alu2_turn_enabled.
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(define_insn "ls2_alu2_turn_enabled_insn"
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[(unspec [(const_int 0)] UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN)]
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"TUNE_LOONGSON_2EF"
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{ gcc_unreachable (); }
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[(set_attr "ls2_turn_type" "alu2")])
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(define_insn_reservation "ls2_alu2_turn_enabled" 0
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(eq_attr "ls2_turn_type" "alu2")
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"ls2_alu2_turn_enabled")
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;; Subscribe ls2_falu1_turn_enabled.
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(define_insn "ls2_falu1_turn_enabled_insn"
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[(unspec [(const_int 0)] UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN)]
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"TUNE_LOONGSON_2EF"
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{ gcc_unreachable (); }
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[(set_attr "ls2_turn_type" "falu1")])
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(define_insn_reservation "ls2_falu1_turn_enabled" 0
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(eq_attr "ls2_turn_type" "falu1")
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"ls2_falu1_turn_enabled")
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;; Subscribe ls2_falu2_turn_enabled.
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(define_insn "ls2_falu2_turn_enabled_insn"
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[(unspec [(const_int 0)] UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN)]
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"TUNE_LOONGSON_2EF"
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{ gcc_unreachable (); }
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[(set_attr "ls2_turn_type" "falu2")])
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(define_insn_reservation "ls2_falu2_turn_enabled" 0
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(eq_attr "ls2_turn_type" "falu2")
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"ls2_falu2_turn_enabled")
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;; Automaton for memory operations.
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(define_automaton "ls2_mem")
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;; Memory unit.
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(define_query_cpu_unit "ls2_mem" "ls2_mem")
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;; Reservation for integer instructions.
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(define_insn_reservation "ls2_alu" 2
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "arith,condmove,const,logical,mfhilo,move,
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mthilo,nop,shift,signext,slt"))
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"ls2_alu")
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;; Reservation for branch instructions.
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(define_insn_reservation "ls2_branch" 2
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "branch,jump,call,trap"))
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"ls2_alu1")
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;; Reservation for integer multiplication instructions.
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(define_insn_reservation "ls2_imult" 5
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "imul,imul3nc"))
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"ls2_alu2,ls2_alu2_core")
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;; Reservation for integer division / remainder instructions.
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;; These instructions use the SRT algorithm and hence take 2-38 cycles.
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(define_insn_reservation "ls2_idiv" 20
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "idiv,idiv3"))
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"ls2_alu2,ls2_alu2_core*18")
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;; Reservation for memory load instructions.
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(define_insn_reservation "ls2_load" 5
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "load,fpload,mfc,mtc"))
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"ls2_mem")
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(define_insn_reservation "ls2_prefetch" 0
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "prefetch,prefetchx"))
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"ls2_mem")
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;; Reservation for memory store instructions.
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;; With stores we assume they don't alias with dependent loads.
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;; Therefore we set the latency to zero.
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(define_insn_reservation "ls2_store" 0
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "store,fpstore"))
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"ls2_mem")
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;; Reservation for floating-point instructions of latency 3.
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(define_insn_reservation "ls2_fp3" 3
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "fabs,fneg,fcmp,fmove"))
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"ls2_falu1")
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;; Reservation for floating-point instructions of latency 5.
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(define_insn_reservation "ls2_fp5" 5
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "fcvt"))
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"ls2_falu1")
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;; Reservation for floating-point instructions that can go
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;; to either of FALU1/2 units.
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(define_insn_reservation "ls2_falu" 7
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "fadd,fmul,fmadd"))
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"ls2_falu")
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;; Reservation for floating-point division / remainder instructions.
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;; These instructions use the SRT algorithm and hence take a variable amount
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;; of cycles:
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;; div.s takes 5-11 cycles
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;; div.d takes 5-18 cycles
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(define_insn_reservation "ls2_fdiv" 9
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "fdiv"))
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"ls2_falu2,ls2_falu2_core*7")
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;; Reservation for floating-point sqrt instructions.
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;; These instructions use the SRT algorithm and hence take a variable amount
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;; of cycles:
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;; sqrt.s takes 5-17 cycles
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;; sqrt.d takes 5-32 cycles
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(define_insn_reservation "ls2_fsqrt" 15
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "fsqrt"))
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"ls2_falu2,ls2_falu2_core*13")
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;; Two consecutive ALU instructions.
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(define_insn_reservation "ls2_multi" 4
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "multi"))
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"(ls2_alu1,ls2_alu2_core)|(ls2_alu2,ls2_alu1_core)")
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;; Reservation for everything else. Normally, this reservation
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;; will only be used to handle cases like compiling for non-loongson
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;; CPUs with -mtune=loongson2?.
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;;
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;; This reservation depends upon the fact that DFA will check
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;; reservations in the same order as they appear in the file.
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(define_insn_reservation "ls2_unknown" 1
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(eq_attr "cpu" "loongson_2e,loongson_2f")
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"ls2_alu1_core+ls2_alu2_core+ls2_falu1_core+ls2_falu2_core+ls2_mem")
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