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[commtech] Fix cache line size 

Cache line size in current processors (at least the one used for tests:
cerclon) is 64 bytes, not 128. Thus modifying the declaration in
commtech.h
This commit is contained in:
Thomas Preud'homme 2011-01-25 17:25:38 +01:00
parent c3aad28ad5
commit aef40ff651
1 changed files with 1 additions and 1 deletions
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communication_techniques/include/commtech.h
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@ -1,7 +1,7 @@
#ifndef _COMMTECH_H_
#define _COMMTECH_H_ 1
#define CACHE_LINE_SIZE 128
#define CACHE_LINE_SIZE 64
#define BUF_SIZE CACHE_LINE_SIZE
#define likely(x) __builtin_expect(!!(x), 1)